{"title":"A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart SoCs","authors":"Michele Caselli, E. Tiurin, S. Stanzione, A. Boni","doi":"10.1109/icecs53924.2021.9665463","DOIUrl":null,"url":null,"abstract":"This paper presents a novel architecture of a self-calibrating programmable voltage reference with nanoampere current consumption. The output voltage is generated by a programmable impedance matrix, based on MOS transistors and resistors, and periodically calibrated with a duty-cycled bandgap. In application domains where the temperature exhibits a low rate-of-change, an average current consumption of 6.5 nA is achieved, largely outperforming all the previously reported switched-capacitor or floating-gate architectures. Implemented in 55-nm CMOS technology, the reference exhibits a 0.4-to-2.5-V output voltage range, over the −20 to +80°C temperature range.","PeriodicalId":448558,"journal":{"name":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/icecs53924.2021.9665463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a novel architecture of a self-calibrating programmable voltage reference with nanoampere current consumption. The output voltage is generated by a programmable impedance matrix, based on MOS transistors and resistors, and periodically calibrated with a duty-cycled bandgap. In application domains where the temperature exhibits a low rate-of-change, an average current consumption of 6.5 nA is achieved, largely outperforming all the previously reported switched-capacitor or floating-gate architectures. Implemented in 55-nm CMOS technology, the reference exhibits a 0.4-to-2.5-V output voltage range, over the −20 to +80°C temperature range.