An on-chip smart memory for a data flow CPU

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI:10.1109/VLSIC.1989.1037519

G. Uvieghara, Y. Nakagome, D. Jeong, D. Hodges

引用次数: 4

Abstract

Ahtract-Register Alias Table (RAT) is a smart memory that is embedded in HPSm (High-Performance Substrate), a Berkeley data-flow CPU. It is a multiport memory that has content addressability and support for branch prediction and exception handling, in addition to conventional READ and WRITE operations. An experimental 1240-bit smart memory chip is implemented in a 1.6-pm double-metal scalable CMOS process. This memory performs 15 operations within a cycle time of 100 ns, has 34 658 transistors, occupies an area of 3.8 mm X 5.2 mm, and dissipates 0.51 W I117 [a.

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数据流CPU的片上智能内存

RAT (Ahtract-Register Alias Table)是一种嵌入在高性能基板(HPSm)中的智能内存，HPSm是一种Berkeley数据流CPU。它是一种多端口内存，除了常规的READ和WRITE操作外，还具有内容可寻址性，并支持分支预测和异常处理。采用1.6 pm双金属可扩展CMOS工艺实现了实验性1240位智能存储芯片。该存储器在100 ns的周期时间内执行15次操作，具有34658个晶体管，占地3.8 mm X 5.2 mm，功耗为0.51 W I117 [a]。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Symposium 1989 on VLSI Circuits

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