Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs

Abstract

This work reports, for the first time, experimental results of asymmetric self-cascode FD SOI n and pMOSFETs operating at liquid helium temperature. The results show that the improved analog performance obtained by this architecture at room temperature is maintained even for such extreme low temperature, promoting the reduction of impact ionization and parasitic bipolar effects, which may even be suppressed, depending on the threshold voltages of the devices. Although the use of A-SC may cause a small (5-10% for nMOS devices) decrease of the unit-gain frequency at certain bias conditions, the output conductance reduction in A-SC results in the rise of the intrinsic voltage gain that has shown to increase by up to 32 dB and 30 dB for A-SC n and pMOSFETs, respectively, in comparison to ST at 4.2K. The gain improvement at 4.2K has shown to be larger than at 300K at the same current level.