High Efficient Architecture of Polynomial Multiplier with Variable Parameter Based on 2KNTT

Hui-qin Li, Tao Chen, Aijun Wu, Chao-xing Xu, Wei Li, Longmei Nan
{"title":"High Efficient Architecture of Polynomial Multiplier with Variable Parameter Based on 2KNTT","authors":"Hui-qin Li, Tao Chen, Aijun Wu, Chao-xing Xu, Wei Li, Longmei Nan","doi":"10.1109/APCCAS55924.2022.10090300","DOIUrl":null,"url":null,"abstract":"In July 2022, among the finalists for the fourth round of NIST's post-quantum public key cryptography, lattice-based algorithms using NTT to implement polynomial multiplication are CRYSTALS-KYBER and CRYSTALS-Dilithium. Therefore, in this paper, we design an efficient structure for polynomial multiplication based on the 2KNTT method for the purpose of improving the practical performance and satisfying variable parameters for these two algorithms. According to the existing 2KNTT algorithm, an eight-way parallel practical model that adapts to the requirements of the algorithm is designed under the premise of determining the storage granularity in advance. Specifically, the modulo multiplication unit can meet the operation of different moduli at the same time, and the control unit can meet the requirements of different number of terms. Experimental results show that this design can meet the polynomial multiplication with modulus 12~32 bits, term number 128, 256, 512, 1024, and modulus polynomial number $x^{n}+1$, in which it takes 2052 cycles to perform a polynomial multiplication operation with the maximum parameter (n=1024, q=8380417).","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

In July 2022, among the finalists for the fourth round of NIST's post-quantum public key cryptography, lattice-based algorithms using NTT to implement polynomial multiplication are CRYSTALS-KYBER and CRYSTALS-Dilithium. Therefore, in this paper, we design an efficient structure for polynomial multiplication based on the 2KNTT method for the purpose of improving the practical performance and satisfying variable parameters for these two algorithms. According to the existing 2KNTT algorithm, an eight-way parallel practical model that adapts to the requirements of the algorithm is designed under the premise of determining the storage granularity in advance. Specifically, the modulo multiplication unit can meet the operation of different moduli at the same time, and the control unit can meet the requirements of different number of terms. Experimental results show that this design can meet the polynomial multiplication with modulus 12~32 bits, term number 128, 256, 512, 1024, and modulus polynomial number $x^{n}+1$, in which it takes 2052 cycles to perform a polynomial multiplication operation with the maximum parameter (n=1024, q=8380417).
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于2KNTT的变参数多项式乘法器的高效结构
2022年7月,在第四轮NIST后量子公钥加密的决赛中,使用NTT实现多项式乘法的基于晶格的算法是CRYSTALS-KYBER和CRYSTALS-Dilithium。因此,本文基于2KNTT方法设计了一种高效的多项式乘法结构,以提高这两种算法的实用性能和满足可变参数。根据现有的2KNTT算法,在事先确定存储粒度的前提下,设计了一个适应算法要求的八路并行实用模型。具体来说,模乘法单元可以同时满足不同模的运算,控制单元可以满足不同项数的要求。实验结果表明,本设计能够满足模数为12~32位,项数为128、256、512、1024,模数为x^{n}+1$的多项式乘法运算,其中最大参数(n=1024, q=8380417)的多项式乘法运算需要2052个周期。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout An Eigen-decomposition Free Method for Computing Graph Fourier Transform Centrality A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE A Vector Pair Based DWA Algorithm for Linearity Enhancement of CDACs in the NS-SAR ADC Optimal Evasive Path Planning with Velocity Constraint
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1