Quantifying the benefits of cycle time reduction in semiconductor wafer fabrication

Abstract

In recent years, semiconductor manufacturing has become extremely complex due to device size reduction. Hence the manufacturing cycle time, also called turn around time (TAT), which is defined as the time required from wafer input through probing test, becomes longer year by year. This renders the delay between process defect occurrence and detection a significant problem. On the other hand, customer demands for faster delivery are increasing because their product life cycles are getting shorter. Therefore, TAT reduction is important for semiconductor manufacturers not only to satisfy customer requirements, but also to remain competitive in their market. This paper examines the financial benefits of TAT reduction using stochastic simulation.