Layout-level design for testability rules for a CMOS cell library

Abstract

In CMOS technology there are some faults (opens and shorts) that are hard to detect or even undetectable. For this reason layout level design for testability (LLDFT) rules have been developed. These rules prevent the faults or reduce the appearance probability of them. The purpose of this work is to apply a practical set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cells.<>