MOSFET stacked-pair test structure for mismatch evaluation by estimating the on-resistance ratio

Abstract

This work describes a procedure for evaluating the mismatch between MOSFET transistors in a test array and connected as stacked-pairs. The transistor mismatch is characterized by measuring the gate voltage dependence of the DC voltage established at the middle node of the common-gate MOSFET stacked-pair. This procedure is modeled as the on-resistance ratio of these two transistors and it is performed by two simple measurements. Various pieces of information on the MOSFET mismatch characteristics (e.g., channel length variation and threshold voltage variation) can be extracted. The test structure was manufactured in 180nm CMOS technology, and the test array was designed to allow a large number of MOSFET stacked-pairs, from transistors placed in different parts of the layout to vary gradually the distance of the paired FETs.