Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456559
Juan Pablo Martinez Brito, M. Lubaszewski, S. Bampi
This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 μm2 in each test chip.
{"title":"Within-die and die-to-die variability on 65nm CMOS : oscillators experimental results","authors":"Juan Pablo Martinez Brito, M. Lubaszewski, S. Bampi","doi":"10.1109/VARI.2015.7456559","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456559","url":null,"abstract":"This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different chip samples, all from a single MOSIS Multi-Project-wafer in a commercial 65nm CMOS process. All ROs were measured with varying power supply voltages, from nominal VDD (1.2V) down to nearthreshold (0.45V), resulting in a sample space of 18.432 points of interest. Statistical analysis results are shown regarding each RO stage size, the applied power supply and the correlation of both to the WID and D2D variations. The increase on D2D and WID coefficients of variations at the near-threshold supplies is very significant, as explained by increased delay variability at the moderate inversion regime of the FETs. The 96 test ROs occupy a total area of 200 x 480 μm2 in each test chip.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124917598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456560
Juan Pablo Martinez Brito, M. Lubaszewski, S. Bampi
This work describes a procedure for evaluating the mismatch between MOSFET transistors in a test array and connected as stacked-pairs. The transistor mismatch is characterized by measuring the gate voltage dependence of the DC voltage established at the middle node of the common-gate MOSFET stacked-pair. This procedure is modeled as the on-resistance ratio of these two transistors and it is performed by two simple measurements. Various pieces of information on the MOSFET mismatch characteristics (e.g., channel length variation and threshold voltage variation) can be extracted. The test structure was manufactured in 180nm CMOS technology, and the test array was designed to allow a large number of MOSFET stacked-pairs, from transistors placed in different parts of the layout to vary gradually the distance of the paired FETs.
{"title":"MOSFET stacked-pair test structure for mismatch evaluation by estimating the on-resistance ratio","authors":"Juan Pablo Martinez Brito, M. Lubaszewski, S. Bampi","doi":"10.1109/VARI.2015.7456560","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456560","url":null,"abstract":"This work describes a procedure for evaluating the mismatch between MOSFET transistors in a test array and connected as stacked-pairs. The transistor mismatch is characterized by measuring the gate voltage dependence of the DC voltage established at the middle node of the common-gate MOSFET stacked-pair. This procedure is modeled as the on-resistance ratio of these two transistors and it is performed by two simple measurements. Various pieces of information on the MOSFET mismatch characteristics (e.g., channel length variation and threshold voltage variation) can be extracted. The test structure was manufactured in 180nm CMOS technology, and the test array was designed to allow a large number of MOSFET stacked-pairs, from transistors placed in different parts of the layout to vary gradually the distance of the paired FETs.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456562
Francisco Veirano, F. Silveira, Lirida Navinery
Intrinsic noise has been predicted as a limit to CMOS scaling. If this is the case, the effect would be more severe at low supply voltages, such as the ones applied in subthreshold digital circuits. In this work the effect of intrinsic noise in subthreshold digital nanoscale CMOS is analysed for the first time. Key issues such as variability and the actual bandwidth of the studied circuits are taken into account. Most of previous works overestimate the impact of intrinsic noise due to the use of simplified models of the MOS transistor. BSIM4 transistor model and PTM model files are used in order to correctly calculate noise RMS voltage at the output node of an inverter, which has not been done before in the subthreshold region. Technology scaling impact is explored by simulating technology nodes from 130 nm down to 16 nm and considering variability down to 32 nm. Simulation results show that variability strongly increases the minimum operating voltage of subthreshold digital nanoscale CMOS and thus making intrinsic noise not a problem, at least down to 32 nm, since commutation voltage maintains high enough to achieve negligible failure rates.
{"title":"Is intrinsic noise a limiting factor for subthreshold digital logic in nanoscale CMOS?","authors":"Francisco Veirano, F. Silveira, Lirida Navinery","doi":"10.1109/VARI.2015.7456562","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456562","url":null,"abstract":"Intrinsic noise has been predicted as a limit to CMOS scaling. If this is the case, the effect would be more severe at low supply voltages, such as the ones applied in subthreshold digital circuits. In this work the effect of intrinsic noise in subthreshold digital nanoscale CMOS is analysed for the first time. Key issues such as variability and the actual bandwidth of the studied circuits are taken into account. Most of previous works overestimate the impact of intrinsic noise due to the use of simplified models of the MOS transistor. BSIM4 transistor model and PTM model files are used in order to correctly calculate noise RMS voltage at the output node of an inverter, which has not been done before in the subthreshold region. Technology scaling impact is explored by simulating technology nodes from 130 nm down to 16 nm and considering variability down to 32 nm. Simulation results show that variability strongly increases the minimum operating voltage of subthreshold digital nanoscale CMOS and thus making intrinsic noise not a problem, at least down to 32 nm, since commutation voltage maintains high enough to achieve negligible failure rates.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"11 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123874929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456557
G. Jacquemod, Zhaopeng Wei, Jad Modad, Y. Leduc, P. Lorenzini, F. Hameau, E. de Foucauld
This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary cells allow us to implement back-gate auto-biasing feedback without adding transistors and to realize a quadrature ring oscillator with an even number of inverters.
{"title":"Study and reduction of variability in 28 nm FDSOI technology","authors":"G. Jacquemod, Zhaopeng Wei, Jad Modad, Y. Leduc, P. Lorenzini, F. Hameau, E. de Foucauld","doi":"10.1109/VARI.2015.7456557","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456557","url":null,"abstract":"This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary cells allow us to implement back-gate auto-biasing feedback without adding transistors and to realize a quadrature ring oscillator with an even number of inverters.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456553
H. Abbas, Mark Zwolinski, Basel Halak
There is growing concern about time-dependent performance variations of CMOS devices due to ageing-induced delay degradation. One of the main causes of ageing is Negative Bias Temperature Instability (NBTI). Existing models which predict the impact of NBTI on overall system performance assume a generic stress-recovery ratio of input signals of 50%. Such an assumption can cause misleading predictions about how a circuit's performance will degrade over time and more importantly which parts of the system will be most affected. This work develops a novel NBTI ageing analysis which is based on accurate calculations of the stress-recovery ratios for applicationspecific systems. The proposed method is employed to predict the ageing of an ARM processor synthesised to 90nm technology. Our results show the proposed ageing analysis techniques can significantly reduce prediction errors (e.g. 39% for one of the critical paths) compared to the generic models, it can also identify more accurately the parts of the system which are most vulnerable to ageing.
{"title":"An application-specific NBTI ageing analysis method","authors":"H. Abbas, Mark Zwolinski, Basel Halak","doi":"10.1109/VARI.2015.7456553","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456553","url":null,"abstract":"There is growing concern about time-dependent performance variations of CMOS devices due to ageing-induced delay degradation. One of the main causes of ageing is Negative Bias Temperature Instability (NBTI). Existing models which predict the impact of NBTI on overall system performance assume a generic stress-recovery ratio of input signals of 50%. Such an assumption can cause misleading predictions about how a circuit's performance will degrade over time and more importantly which parts of the system will be most affected. This work develops a novel NBTI ageing analysis which is based on accurate calculations of the stress-recovery ratios for applicationspecific systems. The proposed method is employed to predict the ageing of an ARM processor synthesised to 90nm technology. Our results show the proposed ageing analysis techniques can significantly reduce prediction errors (e.g. 39% for one of the critical paths) compared to the generic models, it can also identify more accurately the parts of the system which are most vulnerable to ageing.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127734563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456554
A. Chua, R. J. Maestro, M. V. Alba, W. V. Lofamia, B. R. Pelayo, K. B. Fabay, J. Jardin, K. J. C. Jocson, J. Madamba, J. Hizon, L. Alarcón
The delay dependency of digital circuits on process, voltage and temperature variations are usually compensated by using safety margins that set the limit of operating supply voltage or clock frequency. Razor enables the processor to operate beyond this safety margin through the utilization of error detection and recovery circuits. In this paper, a single chip dual ARM9 core solution, with and without Razor, is implemented in 65nm CMOS to accurately characterize the added resiliency introduced by Razor. Functionality testing on the same operating environment allows for a fair characterization by isolating delay dependencies caused by PVT variations.
{"title":"Delay variation compensation through error correction using razor","authors":"A. Chua, R. J. Maestro, M. V. Alba, W. V. Lofamia, B. R. Pelayo, K. B. Fabay, J. Jardin, K. J. C. Jocson, J. Madamba, J. Hizon, L. Alarcón","doi":"10.1109/VARI.2015.7456554","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456554","url":null,"abstract":"The delay dependency of digital circuits on process, voltage and temperature variations are usually compensated by using safety margins that set the limit of operating supply voltage or clock frequency. Razor enables the processor to operate beyond this safety margin through the utilization of error detection and recovery circuits. In this paper, a single chip dual ARM9 core solution, with and without Razor, is implemented in 65nm CMOS to accurately characterize the added resiliency introduced by Razor. Functionality testing on the same operating environment allows for a fair characterization by isolating delay dependencies caused by PVT variations.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130439390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456561
F. Roger, A. Singulani, S. Carniello, L. Filipovic, S. Selberherr
We describe a global methodology for the extraction and the quantification of the effects of the most relevant equipment parameters involved in TSV processing. With a specific focus on the DRIE step of the TSVs' fabrication, we propose a dedicated simulation flow describing the distribution of the species over the wafer inside the etching chamber, the physical plasma simulation of polymer deposition and etching loops, and the electrical performance simulation of the resulting structures. Statistical techniques such as Pareto Graphs and Design of Experiments are used for the extraction of the most relevant equipment parameters on the electrical and metal stress responses.
{"title":"Global statistical methodology for the analysis of equipment parameter effects on TSV formation","authors":"F. Roger, A. Singulani, S. Carniello, L. Filipovic, S. Selberherr","doi":"10.1109/VARI.2015.7456561","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456561","url":null,"abstract":"We describe a global methodology for the extraction and the quantification of the effects of the most relevant equipment parameters involved in TSV processing. With a specific focus on the DRIE step of the TSVs' fabrication, we propose a dedicated simulation flow describing the distribution of the species over the wafer inside the etching chamber, the physical plasma simulation of polymer deposition and etching loops, and the electrical performance simulation of the resulting structures. Statistical techniques such as Pareto Graphs and Design of Experiments are used for the extraction of the most relevant equipment parameters on the electrical and metal stress responses.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131057557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456558
Rida Kheirallah, N. Azémard, G. Ducharme
Due to the effects of the Moore's law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On- Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.
{"title":"Energy study for 28nm FDSOI technology","authors":"Rida Kheirallah, N. Azémard, G. Ducharme","doi":"10.1109/VARI.2015.7456558","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456558","url":null,"abstract":"Due to the effects of the Moore's law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On- Insulator (FDSOI) technology is one of the main contenders for deep submicron devices as they can operate at low voltage with superior energy efficiency compared with bulk CMOS. In this paper, we study the static energy on 28nm FDSOI devices to implement sub-threshold circuits. Study of delay vs. static power trade-off reveals the FDSOI robustness with respect to process variations.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128734684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456563
H. Yamauchi, Worawit Somha
A noise suppressing filter design technique to reduce deconvolution error of both-directions downward sloped asymmetrical long-tail distribution of the Random Telegraph Noise (RTN) is proposed. The filter is used in Lucy-Richardson-deconvolution (LRDec) iteration process. The deconvolution is required for inversely analyzing RTN long tail distribution effects on VLSI time-dependent operating margin. The proposed noise suppressing filters avoid unwanted phase misalignment between the distribution curves of feedback gain and deconvolution target for right and left tails. This results in reduction of its relative deconvolution errors by about 12-fold compared with the conventional LRDec. The accuracy of the fail-bit-count (FBC) prediction is increased by about 100-fold.
{"title":"A noise suppressing filter design for reducing deconvolution error of both-directions downward sloped asymmeric RTN long-tail distributions","authors":"H. Yamauchi, Worawit Somha","doi":"10.1109/VARI.2015.7456563","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456563","url":null,"abstract":"A noise suppressing filter design technique to reduce deconvolution error of both-directions downward sloped asymmetrical long-tail distribution of the Random Telegraph Noise (RTN) is proposed. The filter is used in Lucy-Richardson-deconvolution (LRDec) iteration process. The deconvolution is required for inversely analyzing RTN long tail distribution effects on VLSI time-dependent operating margin. The proposed noise suppressing filters avoid unwanted phase misalignment between the distribution curves of feedback gain and deconvolution target for right and left tails. This results in reduction of its relative deconvolution errors by about 12-fold compared with the conventional LRDec. The accuracy of the fail-bit-count (FBC) prediction is increased by about 100-fold.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121112620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/VARI.2015.7456555
Hernán Aparicio, P. Ituero, M. López-Vallejo
Power supply noise in current nanometer technologies represents a growing risk, specially because of the uncertainties it produces in the critical paths delays which can result in erroneous computations. To tackle with these issues and to have a better power management, power supply monitors are necessary. Traditional approaches use an external reference or are very sensitive to temperature and process variations. In this work we propose a monitor that works without an external reference and is hardened against thermal and process variations. The sensor was designed in the 40 nm CMOS technology node, operating at 1.1 V and has been validated for a temperature range of -40 °C to 125 °C covering all process corners. The sensor is able to detect voltage fluctuations of at least 45 mV, wider than 300 ps in the worst technology corner with a maximum latency of 600 ps and an energy consumption per measurement of 2.64 pJ.
{"title":"2.64 pJ reference-free power supply monitor with a wide temperature range","authors":"Hernán Aparicio, P. Ituero, M. López-Vallejo","doi":"10.1109/VARI.2015.7456555","DOIUrl":"https://doi.org/10.1109/VARI.2015.7456555","url":null,"abstract":"Power supply noise in current nanometer technologies represents a growing risk, specially because of the uncertainties it produces in the critical paths delays which can result in erroneous computations. To tackle with these issues and to have a better power management, power supply monitors are necessary. Traditional approaches use an external reference or are very sensitive to temperature and process variations. In this work we propose a monitor that works without an external reference and is hardened against thermal and process variations. The sensor was designed in the 40 nm CMOS technology node, operating at 1.1 V and has been validated for a temperature range of -40 °C to 125 °C covering all process corners. The sensor is able to detect voltage fluctuations of at least 45 mV, wider than 300 ps in the worst technology corner with a maximum latency of 600 ps and an energy consumption per measurement of 2.64 pJ.","PeriodicalId":299950,"journal":{"name":"2015 International Workshop on CMOS Variability (VARI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131231536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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