Characterizing individual gate power sensitivity in low power design

Abstract

Accuracy of gate level power estimation is very important because the decisions for power optimization are made based on estimation. In addition to the logical values of the primary inputs and the state of the circuit, there are a wide variety of other parameters that affect the switching activity of individual gates. Some of these factors include layout considerations such as transistor sizes, process considerations such as the supply voltage or parameters such as T/sub ox/, and finally timing considerations such as the gate delay model and the arrival time of the input signals. in this paper, we present empirical data that quantifies the relative impact of these factors on a wide variety of example circuits. The data indicates that if these factors are not taken into account, most gate level power estimates will be very inaccurate, and consequently most power estimation techniques will be of limited use.