{"title":"A Built In Test circuit for waveform classification at high frequencies","authors":"K. Poulos, T. Haniotakis","doi":"10.1109/NATW49237.2020.9153078","DOIUrl":null,"url":null,"abstract":"We introduce a new Build In Test (BIT) signature generator for functional verification and output classification of RF integrated circuits. The proposed circuit is a single rectifier-based MOS transistor, with the substrate and gate independently biased to control source terminal voltage range, followed by a passive RC filter. The proposed technique correlates the Circuit Under Test (CUT) characteristics with the dc voltage provided at the output of the BIT circuit. The output from the proposed circuit is used as signature from which we verify the performance specifications and also characterize the CUT output waveform with respect to amplitude and shape. In normal operation the proposed low cost test scheme ensures the minimum effect at the performance of the measured circuit under test since the only additional load is the source of the MOS transistor attached to it.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"33 23","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NATW49237.2020.9153078","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We introduce a new Build In Test (BIT) signature generator for functional verification and output classification of RF integrated circuits. The proposed circuit is a single rectifier-based MOS transistor, with the substrate and gate independently biased to control source terminal voltage range, followed by a passive RC filter. The proposed technique correlates the Circuit Under Test (CUT) characteristics with the dc voltage provided at the output of the BIT circuit. The output from the proposed circuit is used as signature from which we verify the performance specifications and also characterize the CUT output waveform with respect to amplitude and shape. In normal operation the proposed low cost test scheme ensures the minimum effect at the performance of the measured circuit under test since the only additional load is the source of the MOS transistor attached to it.