Pub Date : 2020-06-01DOI: 10.1109/NATW49237.2020.9153077
Naznin Akter, M. Karabiyik, M. Shur, J. Suarez, N. Pala
Increasing complexity of digital and mixed-signal systems makes establishing the authenticity of a chip to be a challenging problem. We present a new terahertz testing technique for non-destructive identification of genuine integrated circuits, in package, in-situ and either with no or under bias, by measuring their response to scanning terahertz and sub-terahertz radiation at the circuit pins. This novel, patent pending non-invasive nondestructive technology when merged with Artificial Intelligence (AI) engine will evolve and self-improve with each test cycle. By establishing and AI processing of the THz scanning signatures of reliable devices and circuits and comparing this signatures with devices under test using AI, this technology could be also used for reliability and lifetime prediction.
{"title":"AI Powered THz VLSI Testing Technology","authors":"Naznin Akter, M. Karabiyik, M. Shur, J. Suarez, N. Pala","doi":"10.1109/NATW49237.2020.9153077","DOIUrl":"https://doi.org/10.1109/NATW49237.2020.9153077","url":null,"abstract":"Increasing complexity of digital and mixed-signal systems makes establishing the authenticity of a chip to be a challenging problem. We present a new terahertz testing technique for non-destructive identification of genuine integrated circuits, in package, in-situ and either with no or under bias, by measuring their response to scanning terahertz and sub-terahertz radiation at the circuit pins. This novel, patent pending non-invasive nondestructive technology when merged with Artificial Intelligence (AI) engine will evolve and self-improve with each test cycle. By establishing and AI processing of the THz scanning signatures of reliable devices and circuits and comparing this signatures with devices under test using AI, this technology could be also used for reliability and lifetime prediction.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114704382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NATW49237.2020.9153078
K. Poulos, T. Haniotakis
We introduce a new Build In Test (BIT) signature generator for functional verification and output classification of RF integrated circuits. The proposed circuit is a single rectifier-based MOS transistor, with the substrate and gate independently biased to control source terminal voltage range, followed by a passive RC filter. The proposed technique correlates the Circuit Under Test (CUT) characteristics with the dc voltage provided at the output of the BIT circuit. The output from the proposed circuit is used as signature from which we verify the performance specifications and also characterize the CUT output waveform with respect to amplitude and shape. In normal operation the proposed low cost test scheme ensures the minimum effect at the performance of the measured circuit under test since the only additional load is the source of the MOS transistor attached to it.
{"title":"A Built In Test circuit for waveform classification at high frequencies","authors":"K. Poulos, T. Haniotakis","doi":"10.1109/NATW49237.2020.9153078","DOIUrl":"https://doi.org/10.1109/NATW49237.2020.9153078","url":null,"abstract":"We introduce a new Build In Test (BIT) signature generator for functional verification and output classification of RF integrated circuits. The proposed circuit is a single rectifier-based MOS transistor, with the substrate and gate independently biased to control source terminal voltage range, followed by a passive RC filter. The proposed technique correlates the Circuit Under Test (CUT) characteristics with the dc voltage provided at the output of the BIT circuit. The output from the proposed circuit is used as signature from which we verify the performance specifications and also characterize the CUT output waveform with respect to amplitude and shape. In normal operation the proposed low cost test scheme ensures the minimum effect at the performance of the measured circuit under test since the only additional load is the source of the MOS transistor attached to it.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"33 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132063488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NATW49237.2020.9153075
S. Moss, Elanchezhian Veeramani, Joris Angelo Sundaram Jerome
PIM is a form of intermodulation distortion that occurs in passive components. It is an unwanted signal created by the mixing of two or more RF signals, caused by the nonlinearity of the passive components in the RF path. PIM has become a big concern in the wireless and communication industry, with the introduction of 5G standards. The most demanding requirement of the linearity of the switches in an RF system is the out-of-band blocking performance. The blocking characteristic is a measure of the receiver's ability to pick up the wanted signal in the presence of an unwanted interfering signal, without causing a degradation in the performance. The rise of unwanted signals in the receiver path increase the noise level of the receiver, thereby degrading the quality of the communication signals as well as affecting the receiver sensitivity. The paper describes the way PIM measurements are performed in our lab and highlight how Multiband PIM measurements are carried out in a very efficient way, saving the time invested in setup, calibration and measurements of data, using meticulous techniques which ultimately lead to a better result.
{"title":"Passive Intermodulation (PIM) Test and Measurement","authors":"S. Moss, Elanchezhian Veeramani, Joris Angelo Sundaram Jerome","doi":"10.1109/NATW49237.2020.9153075","DOIUrl":"https://doi.org/10.1109/NATW49237.2020.9153075","url":null,"abstract":"PIM is a form of intermodulation distortion that occurs in passive components. It is an unwanted signal created by the mixing of two or more RF signals, caused by the nonlinearity of the passive components in the RF path. PIM has become a big concern in the wireless and communication industry, with the introduction of 5G standards. The most demanding requirement of the linearity of the switches in an RF system is the out-of-band blocking performance. The blocking characteristic is a measure of the receiver's ability to pick up the wanted signal in the presence of an unwanted interfering signal, without causing a degradation in the performance. The rise of unwanted signals in the receiver path increase the noise level of the receiver, thereby degrading the quality of the communication signals as well as affecting the receiver sensitivity. The paper describes the way PIM measurements are performed in our lab and highlight how Multiband PIM measurements are carried out in a very efficient way, saving the time invested in setup, calibration and measurements of data, using meticulous techniques which ultimately lead to a better result.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122788856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NATW49237.2020.9153080
S. Rauch, Dongho Lee, A. Vert, Roy Gupta
The power limits due to thermal runaway of a germanium PIN photodiode as the O-band $(lambdasimmathbf{1300 nm})$ photodetector component of a silicon photonics technology were characterized under elevated stress conditions. A simplified model is used to project to use condition.
{"title":"Characterization of Thermal Runaway in a Ge Photodiode for Si Photonics","authors":"S. Rauch, Dongho Lee, A. Vert, Roy Gupta","doi":"10.1109/NATW49237.2020.9153080","DOIUrl":"https://doi.org/10.1109/NATW49237.2020.9153080","url":null,"abstract":"The power limits due to thermal runaway of a germanium PIN photodiode as the O-band $(lambdasimmathbf{1300 nm})$ photodetector component of a silicon photonics technology were characterized under elevated stress conditions. A simplified model is used to project to use condition.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117135939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NATW49237.2020.9153082
J. Immanuel, S. Millican
This article presents an artificial neural network-based signal probability predictor for VLSI circuits which considers reconvergent fan-outs. Current testability analysis techniques are useful for inserting test points to improve circuit testability, but reconvergent fan-outs in digital circuits creates inaccurate testability analysis. Conventional testability analysis methods like COP do not consider reconvergent fan-outs and can degrade algorithm results (e.g., test point insertion), while more advanced methods increase analysis time significantly. This study shows training and using artificial neural networks to predict signal probabilities increases post-test point insertion fault coverage compared to using COP, especially in circuits with many reconvergent fan-outs.
{"title":"Calculating Signal Controllability using Neural Networks: Improvements to Testability Analysis and Test Point Insertion","authors":"J. Immanuel, S. Millican","doi":"10.1109/NATW49237.2020.9153082","DOIUrl":"https://doi.org/10.1109/NATW49237.2020.9153082","url":null,"abstract":"This article presents an artificial neural network-based signal probability predictor for VLSI circuits which considers reconvergent fan-outs. Current testability analysis techniques are useful for inserting test points to improve circuit testability, but reconvergent fan-outs in digital circuits creates inaccurate testability analysis. Conventional testability analysis methods like COP do not consider reconvergent fan-outs and can degrade algorithm results (e.g., test point insertion), while more advanced methods increase analysis time significantly. This study shows training and using artificial neural networks to predict signal probabilities increases post-test point insertion fault coverage compared to using COP, especially in circuits with many reconvergent fan-outs.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NATW49237.2020.9153081
P. Paliwoda, M. Toledano-Luque, T. Nigam, F. Guarín, M. Nour, S. Cimino, L. Pantisano, A. Gupta, Oscar Huerta-Gonzalez, M. Hauser, W. Liu, A. Vayshenker, D. Ioannou, D. Lee, L. Jiang, P. Yee, S. Rauch, B. Min
This work presents various device self-heating temperature sensing techniques and discusses their application in device reliability projection. Details of sensor design, technology choice, layout and ambient temperature impact on measurement results are discussed. The sensors produce excellent results which were confirmed through TCAD thermal simulation. Self-heating was studied by varying the number of fins per active region and proximity of sensor to heater was investigated. While most data presented here is on FinFET technology the learning and measurement techniques are applicable to planar technologies. Front-end-of-line (FEOL) reliability mechanism, hot carrier injection (HCI) was studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. Self-heating is also studied for logic circuits by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions conducted on discrete structures.
{"title":"Self-heating characterization and its applications in technology development","authors":"P. Paliwoda, M. Toledano-Luque, T. Nigam, F. Guarín, M. Nour, S. Cimino, L. Pantisano, A. Gupta, Oscar Huerta-Gonzalez, M. Hauser, W. Liu, A. Vayshenker, D. Ioannou, D. Lee, L. Jiang, P. Yee, S. Rauch, B. Min","doi":"10.1109/NATW49237.2020.9153081","DOIUrl":"https://doi.org/10.1109/NATW49237.2020.9153081","url":null,"abstract":"This work presents various device self-heating temperature sensing techniques and discusses their application in device reliability projection. Details of sensor design, technology choice, layout and ambient temperature impact on measurement results are discussed. The sensors produce excellent results which were confirmed through TCAD thermal simulation. Self-heating was studied by varying the number of fins per active region and proximity of sensor to heater was investigated. While most data presented here is on FinFET technology the learning and measurement techniques are applicable to planar technologies. Front-end-of-line (FEOL) reliability mechanism, hot carrier injection (HCI) was studied to show that self-heating effects can impact measurement results and recommendations are given on how to mitigate them. Self-heating is also studied for logic circuits by utilizing ring oscillators with several densities and stage counts to show that self-heating is considerably lower compared to constant voltage stress conditions conducted on discrete structures.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117253347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-06-01DOI: 10.1109/NATW49237.2020.9153079
Marcia Golmohamadi, R. Jurasek, W. Hokenmaier, D. Labrecque, Ruoyu Zhi, Bret Dale, Nibir Islam, Dave Kinney, Angela Johnson
In-memory computing is a propitious solution for overcoming the memory bottleneck for future computer systems. In this work, we present the testing and validation considerations for a programmable artificial neural network (ANN) integrated within a phase change memory (PCM) chip, featuring a Nor-Flash compatible serial peripheral interface (SPI). In this paper, we introduce our method for validating the circuit components specific to the ANN application. In addition, high-density in-memory multi-layer ANNs cannot be manufactured without testing and repair of the memory array itself. Therefore, design for testability (DFT) features commonly used in commodity or embedded memory products must be maintained as well. The combination of these two test/characterization steps alleviates the need to test the actual inference functionality in hardware.
{"title":"Verification and Testing Considerations of an In-Memory AI Chip","authors":"Marcia Golmohamadi, R. Jurasek, W. Hokenmaier, D. Labrecque, Ruoyu Zhi, Bret Dale, Nibir Islam, Dave Kinney, Angela Johnson","doi":"10.1109/NATW49237.2020.9153079","DOIUrl":"https://doi.org/10.1109/NATW49237.2020.9153079","url":null,"abstract":"In-memory computing is a propitious solution for overcoming the memory bottleneck for future computer systems. In this work, we present the testing and validation considerations for a programmable artificial neural network (ANN) integrated within a phase change memory (PCM) chip, featuring a Nor-Flash compatible serial peripheral interface (SPI). In this paper, we introduce our method for validating the circuit components specific to the ANN application. In addition, high-density in-memory multi-layer ANNs cannot be manufactured without testing and repair of the memory array itself. Therefore, design for testability (DFT) features commonly used in commodity or embedded memory products must be maintained as well. The combination of these two test/characterization steps alleviates the need to test the actual inference functionality in hardware.","PeriodicalId":147604,"journal":{"name":"2020 IEEE 29th North Atlantic Test Workshop (NATW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114288350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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