A 350 ps 50 K 0.8 μm BiCMOS gate array with shared bipolar cell structure

H. Hara, Yasuhiro Sugimoto, M. Noda, T. Nagamatsu, Y. Watanabe, Hiroshi Iwai, Y. Niitsu, G. Sasaki, K. Maeguchi
{"title":"A 350 ps 50 K 0.8 μm BiCMOS gate array with shared bipolar cell structure","authors":"H. Hara, Yasuhiro Sugimoto, M. Noda, T. Nagamatsu, Y. Watanabe, Hiroshi Iwai, Y. Niitsu, G. Sasaki, K. Maeguchi","doi":"10.1109/CICC.1989.56712","DOIUrl":null,"url":null,"abstract":"A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"120 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56712","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

Abstract

A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V
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具有共享双极电池结构的350 ps 50 K 0.8 μ m BiCMOS栅极阵列
采用0.8 μm BiCMOS技术,实现了门延迟为350 ps的BiCMOS门阵列。通过共享双极电池结构,实现了最小的栅极延迟和最小的电池面积。栅极延迟几乎相当于0.5 μm纯CMOS栅极阵列的栅极延迟。与0.8 μm纯CMOS电池相比,电池面积仅增加了25%。I/O单元可以在5 V的单电源电压下同时与CMOS、TTL(晶体管-晶体管逻辑)和ECL(发射器耦合逻辑)芯片进行接口
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