Low contact resistance polysilicon plug for halfmicron CMOS technology

Abstract

A polycrystalline silicon (polysilicon) plug was developed for the planarization of high-aspect-ratio contact holes. Using this method, the authors realized a low contact resistance of 118 Omega on p-type and 57 Omega on n-type diffusion layers for 0.6- mu m hole diameter and 0.8- mu m hole depth. Moreover, a shallow source/drain junction of 0.15- mu m depth using rapid thermal annealing (RTA) was obtained. The key issues in this technology are the double (low- and high-energy) ion implantation of boron for the p-type plug and low-temperature insertion and subsequent deposition of polysilicon and dopant activation by RTA in the plugs and diffused layers at the same time.<>