A special purpose coprocessor supporting cell placement and floorplanning algorithms

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56678

R. Kling, P. Banerjee

引用次数: 1

Abstract

A coprocessor supporting a variety of placement and floorplanning algorithms is described. Without special hardware, the CPU time used by placement algorithms for net length computations can reach up to about 50% of the total run time. The proposed coprocessor architecture has special provisions for efficient net length computation which also allow concurrent execution with the main CPU. A prototype chip has been manufactured. The estimated speedup factor is about 40 for wire-length calculations. The chip can easily be integrated into current computer systems and usually requires only minimal changes to existing placement programs

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一个特殊用途的协处理器，支持单元放置和平面规划算法

描述了一种支持多种布局和平面规划算法的协处理器。如果没有特殊的硬件，用于净长度计算的放置算法所使用的CPU时间可以达到总运行时间的50%左右。所提出的协处理器体系结构对有效的网络长度计算有特殊的规定，并且允许与主CPU并发执行。一个原型芯片已经制造出来。对于线长计算，估计的加速因子约为40。这种芯片可以很容易地集成到当前的计算机系统中，通常只需要对现有的安装程序进行最小的更改

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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