{"title":"An area-efficient high-speed Reed-Solomon decoder in 0.25 /spl mu/m CMOS","authors":"A. Strollo, N. Petra, D. Caro, E. Napoli","doi":"10.1109/ESSCIR.2004.1356723","DOIUrl":null,"url":null,"abstract":"In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 /spl mu/m CMOS technology, compares favourably with recently proposed RS decoders.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356723","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a Reed-Solomon (RS) decoder for the widely used (255, 239) code is presented. The circuit exploits both a novel inversion-free Berlekamp-Massey algorithm architecture to solve the key-equation and a new bit-parallel Galois-field multiplier implementation to obtain increased circuit speed. Hardware sharing is widely used to reduce silicon area occupation. The proposed circuit, designed for a 0.25 /spl mu/m CMOS technology, compares favourably with recently proposed RS decoders.
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