{"title":"Use of process simulators to assist in the design of processes for manufacturability","authors":"M.R. Kump, S.W. Mylroie, W. Alexander, A. Walton","doi":"10.1109/ASMC.1990.111214","DOIUrl":null,"url":null,"abstract":"It is shown how semiconductor process simulation. by replacing numerous runsplits, can be a cost-effective way to design technologies for both optimal performance and manufacturability. The use of process and device simulators for designing for manufacturability is illustrated by considering two examples both drawn from experiences in semiconductor manufacturing. The first is the design of a high-sheet-resistivity implanted resistor to minimize its variability. The second is the design of certain aspects of a lightly doped drain (LDD) MOS process both to optimize the intrinsic device performance and to improve its manufacturability.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.1990.111214","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
It is shown how semiconductor process simulation. by replacing numerous runsplits, can be a cost-effective way to design technologies for both optimal performance and manufacturability. The use of process and device simulators for designing for manufacturability is illustrated by considering two examples both drawn from experiences in semiconductor manufacturing. The first is the design of a high-sheet-resistivity implanted resistor to minimize its variability. The second is the design of certain aspects of a lightly doped drain (LDD) MOS process both to optimize the intrinsic device performance and to improve its manufacturability.<>
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