Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111234
A. Resnick, E. Kamieniecki, H. Phelps, Donald A. Jackson
The effect of pull temperature on oxide charge and interface trap density is explored using surface charge analysis (SCA). With this technique, lower pull temperatures were found to result in lower oxide charge and interface trap density levels. The impact of pull temperature on these parameters was found to exist even after a number of additional processing steps. SCA was used to evaluate the individual charge contribution of each step within a process sequence.<>
{"title":"In-line process monitoring using surface charge analysis","authors":"A. Resnick, E. Kamieniecki, H. Phelps, Donald A. Jackson","doi":"10.1109/ASMC.1990.111234","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111234","url":null,"abstract":"The effect of pull temperature on oxide charge and interface trap density is explored using surface charge analysis (SCA). With this technique, lower pull temperatures were found to result in lower oxide charge and interface trap density levels. The impact of pull temperature on these parameters was found to exist even after a number of additional processing steps. SCA was used to evaluate the individual charge contribution of each step within a process sequence.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132929204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111217
E. H. Nicollian, S.-s. Chen, R. Tsu
An expert system for monitoring VLSI and ULSI integrated circuit process parameters which is based on the concepts of the charge-capacitance method is described. The process parameters determined are oxide leakage current, impedance to establish electric contact quality, oxide layer thickness, semiconductor doping profile, oxide fixed charge density, interface trap density, semiconductor band bending, and threshold voltage of a MOSFET. Instrumentation and measurement are discussed.<>
{"title":"An expert system for process monitoring, diagnostics and control (VLSI and ULSI circuits)","authors":"E. H. Nicollian, S.-s. Chen, R. Tsu","doi":"10.1109/ASMC.1990.111217","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111217","url":null,"abstract":"An expert system for monitoring VLSI and ULSI integrated circuit process parameters which is based on the concepts of the charge-capacitance method is described. The process parameters determined are oxide leakage current, impedance to establish electric contact quality, oxide layer thickness, semiconductor doping profile, oxide fixed charge density, interface trap density, semiconductor band bending, and threshold voltage of a MOSFET. Instrumentation and measurement are discussed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126598540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111209
K.-K. Lin, C. Spanos
A computer-aided-design (CAD) system which has been developed to assist the process engineer in choosing the best compromise between product and equipment performance is described. A formal, systematic methodology that facilities the task of recipe design for low pressure chemical-vapor-deposition (LPCVD) reactors is discussed. Recipe generation via interactive response surface exploration and automatic recipe generation via numerical optimization are discussed.<>
{"title":"Computer-aided recipe generation for LPCVD reactors","authors":"K.-K. Lin, C. Spanos","doi":"10.1109/ASMC.1990.111209","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111209","url":null,"abstract":"A computer-aided-design (CAD) system which has been developed to assist the process engineer in choosing the best compromise between product and equipment performance is described. A formal, systematic methodology that facilities the task of recipe design for low pressure chemical-vapor-deposition (LPCVD) reactors is discussed. Recipe generation via interactive response surface exploration and automatic recipe generation via numerical optimization are discussed.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115413971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111230
C.B. Barnum, D. Cunningham
A prototype integrated-circuit (IC) computer-aided-manufacturing (CAM) environment to support university education and research programs is described. The CAM system, mask making, and wafer fabrication are discussed. Process controls and the assembly process are described.<>
{"title":"A comprehensive CAM environment for fast-turn IC prototyping","authors":"C.B. Barnum, D. Cunningham","doi":"10.1109/ASMC.1990.111230","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111230","url":null,"abstract":"A prototype integrated-circuit (IC) computer-aided-manufacturing (CAM) environment to support university education and research programs is described. The CAM system, mask making, and wafer fabrication are discussed. Process controls and the assembly process are described.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130464259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111228
S. Illyés, D. Baglee
The methodology of selecting and implementing statistical bin limits (SBLs) for wafer-level testing is discussed. Improvements in the manufacturing flow are discussed. It is found that SBLs can detect process shifts, reject misprocessed material, aid in the streamlining of packaged units, and increase the cost effectiveness of these units. It is shown that the methodology does not add to the complexity of the sort flow. Implementation and maintenance are straightforward and simple.<>
{"title":"Statistical bin limits: an approach to wafer dispositioning in IC fabrication","authors":"S. Illyés, D. Baglee","doi":"10.1109/ASMC.1990.111228","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111228","url":null,"abstract":"The methodology of selecting and implementing statistical bin limits (SBLs) for wafer-level testing is discussed. Improvements in the manufacturing flow are discussed. It is found that SBLs can detect process shifts, reject misprocessed material, aid in the streamlining of packaged units, and increase the cost effectiveness of these units. It is shown that the methodology does not add to the complexity of the sort flow. Implementation and maintenance are straightforward and simple.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"522 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133252146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111214
M.R. Kump, S.W. Mylroie, W. Alexander, A. Walton
It is shown how semiconductor process simulation. by replacing numerous runsplits, can be a cost-effective way to design technologies for both optimal performance and manufacturability. The use of process and device simulators for designing for manufacturability is illustrated by considering two examples both drawn from experiences in semiconductor manufacturing. The first is the design of a high-sheet-resistivity implanted resistor to minimize its variability. The second is the design of certain aspects of a lightly doped drain (LDD) MOS process both to optimize the intrinsic device performance and to improve its manufacturability.<>
{"title":"Use of process simulators to assist in the design of processes for manufacturability","authors":"M.R. Kump, S.W. Mylroie, W. Alexander, A. Walton","doi":"10.1109/ASMC.1990.111214","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111214","url":null,"abstract":"It is shown how semiconductor process simulation. by replacing numerous runsplits, can be a cost-effective way to design technologies for both optimal performance and manufacturability. The use of process and device simulators for designing for manufacturability is illustrated by considering two examples both drawn from experiences in semiconductor manufacturing. The first is the design of a high-sheet-resistivity implanted resistor to minimize its variability. The second is the design of certain aspects of a lightly doped drain (LDD) MOS process both to optimize the intrinsic device performance and to improve its manufacturability.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132243808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111224
B. Duffy, G. Cumming, D. Fletcher
A framework for defect reduction is presented which integrates management commitment, a focused organizational structure, state-of-the-art defect detection and analysis tools, and cooperation between the organizations that affect the quality of the material shipped from a wafer fab line. Considerations for organizational design, the role of the defect reduction engineer, and the defect reduction strategy are presented along with specific defect density, and yield improvement examples.<>
{"title":"Framework for a defect reduction program","authors":"B. Duffy, G. Cumming, D. Fletcher","doi":"10.1109/ASMC.1990.111224","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111224","url":null,"abstract":"A framework for defect reduction is presented which integrates management commitment, a focused organizational structure, state-of-the-art defect detection and analysis tools, and cooperation between the organizations that affect the quality of the material shipped from a wafer fab line. Considerations for organizational design, the role of the defect reduction engineer, and the defect reduction strategy are presented along with specific defect density, and yield improvement examples.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127940270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111225
H. Parks
An effective fast-turnaround postprocess yield-enhancement methodology for custom VLSI which has been developed using a static random access memory (SRAM) and a test element group (TEG) yield vehicle is described. The SRAM/TEG is combined on a single chip providing a unified process-control vehicle. Several examples of visual defect classification using SRAM failure analysis and nonvisual defect characterization from the electrical test monitors are presented. Application of the methodology to yield enhancement efforts for a 1.25- mu m process is presented showing excellent correlation of SRAM and custom circuit yields with a 100* defect density reduction over a two-year period.<>
{"title":"Fast turn around post process yield enhancement for custom VLSI foundries","authors":"H. Parks","doi":"10.1109/ASMC.1990.111225","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111225","url":null,"abstract":"An effective fast-turnaround postprocess yield-enhancement methodology for custom VLSI which has been developed using a static random access memory (SRAM) and a test element group (TEG) yield vehicle is described. The SRAM/TEG is combined on a single chip providing a unified process-control vehicle. Several examples of visual defect classification using SRAM failure analysis and nonvisual defect characterization from the electrical test monitors are presented. Application of the methodology to yield enhancement efforts for a 1.25- mu m process is presented showing excellent correlation of SRAM and custom circuit yields with a 100* defect density reduction over a two-year period.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115412856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111235
R. Potter
A procedure for carrying out a measurement system capability study is presented. The tool is first calibrated against a known standard. Then, the tool's short-term repeatability is determined. A reproducibility evaluation is performed, stability is evaluated over time, and statistical process control is implemented. Key terminology in measurement capability studies is reviewed. Example formulas for a variance components analysis in the simple case where operators are the only source of variation are given.<>
{"title":"Measurement system capability analysis","authors":"R. Potter","doi":"10.1109/ASMC.1990.111235","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111235","url":null,"abstract":"A procedure for carrying out a measurement system capability study is presented. The tool is first calibrated against a known standard. Then, the tool's short-term repeatability is determined. A reproducibility evaluation is performed, stability is evaluated over time, and statistical process control is implemented. Key terminology in measurement capability studies is reviewed. Example formulas for a variance components analysis in the simple case where operators are the only source of variation are given.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130746305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-09-11DOI: 10.1109/ASMC.1990.111237
R. Atherton, F. Turner, L. F. Atherton, M. Pool
A general dynamic model of the cycle-time performance of production integrated processing equipment (PIPE) is discussed. This model has been used to analyze the performance of existing PIPE designs and to derive design enhancements. The performance predictions of the model are compared to measurements of PIPE operation. Case studies of PIPE operation indicate possible production advantages over conventional equipment.<>
{"title":"Performance analysis of multi-process semiconductor manufacturing equipment","authors":"R. Atherton, F. Turner, L. F. Atherton, M. Pool","doi":"10.1109/ASMC.1990.111237","DOIUrl":"https://doi.org/10.1109/ASMC.1990.111237","url":null,"abstract":"A general dynamic model of the cycle-time performance of production integrated processing equipment (PIPE) is discussed. This model has been used to analyze the performance of existing PIPE designs and to derive design enhancements. The performance predictions of the model are compared to measurements of PIPE operation. Case studies of PIPE operation indicate possible production advantages over conventional equipment.<<ETX>>","PeriodicalId":158760,"journal":{"name":"IEEE/SEMI Conference on Advanced Semiconductor Manufacturing Workshop","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133295805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：