{"title":"A Switch Supporting Circuit and Packet Switching for On-Chip Networks","authors":"Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu","doi":"10.1109/DDECS.2006.1649619","DOIUrl":null,"url":null,"abstract":"In this paper, the design of a hybrid switch for on-chip networks in SoC design is presented. This hybrid switch provides both guaranteed and best-effort communication services for network-on-chip architectures. We use the pre-scheduled circuit-switched network to support guaranteed communication service between IPs on the chip. In order to fully utilize the network bandwidth, we further incorporate the packet-switched architecture. Our design has been experimentally implemented using UMC 0.18 mum technology. It has an aggregate bandwidth of 5 times 434MHz times 64 bits = 139 Gb/s. Compared to previous designs, our switch provides high performance with a reasonable cost","PeriodicalId":114139,"journal":{"name":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","volume":"22 6","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2006.1649619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
In this paper, the design of a hybrid switch for on-chip networks in SoC design is presented. This hybrid switch provides both guaranteed and best-effort communication services for network-on-chip architectures. We use the pre-scheduled circuit-switched network to support guaranteed communication service between IPs on the chip. In order to fully utilize the network bandwidth, we further incorporate the packet-switched architecture. Our design has been experimentally implemented using UMC 0.18 mum technology. It has an aggregate bandwidth of 5 times 434MHz times 64 bits = 139 Gb/s. Compared to previous designs, our switch provides high performance with a reasonable cost
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