A. Matsushita, N. Ohashi, K. Inukai, H.J. Shin, S. Sone, K. Sudou, K. Misawa, I. Matsumoto, N. Kobayashi
{"title":"Low damage ashing using H/sub 2//He plasma for porous ultra low-k","authors":"A. Matsushita, N. Ohashi, K. Inukai, H.J. Shin, S. Sone, K. Sudou, K. Misawa, I. Matsumoto, N. Kobayashi","doi":"10.1109/IITC.2003.1219737","DOIUrl":null,"url":null,"abstract":"Novel high-temperature (>150/spl deg/C ) ashing using mixture of H/sub 2/ and He gases (H/sub 2//He) was developed for low damage damascene fabrication of ultra low-k ILDs. Dependence of ashing characteristics on generated plasma configuration and temperature was investigated to optimize the process. Its applications to 320 nm pitch Cu/porous-MSQ (k=2.3) interconnects using 300 mm wafers showed no degradation in leakage currents and wiring capacitance. It is feasible for precise dual damascene etch using the conventional ArF photo resist (PR) mask process towards 65 nm technology node.","PeriodicalId":212619,"journal":{"name":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2003.1219737","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Novel high-temperature (>150/spl deg/C ) ashing using mixture of H/sub 2/ and He gases (H/sub 2//He) was developed for low damage damascene fabrication of ultra low-k ILDs. Dependence of ashing characteristics on generated plasma configuration and temperature was investigated to optimize the process. Its applications to 320 nm pitch Cu/porous-MSQ (k=2.3) interconnects using 300 mm wafers showed no degradation in leakage currents and wiring capacitance. It is feasible for precise dual damascene etch using the conventional ArF photo resist (PR) mask process towards 65 nm technology node.