A 12 ns, CMOS programmable logic device for combinatorial applications

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56694

S. P. Gowni, P. Platt, A. Hawkins, W. Hiltpold, S. Douglass

引用次数: 0

Abstract

A 12-ns, 400-mW programmable logic device implemented in two-layer metal, 0.8-μm CMOS EPROM technology is presented. The device is optimized for combinatorial applications and provides programmable input macrocells for latched, registered, or combinatorial inputs. This device provides 1200 equivalent gates in a 28-pin package, with 13 inputs, 12 I/Os, one VCC, and two VSS pins. Each I/O pin, in addition to the programmable input register, has a product-term-controlled XOR gate for dynamic output polarity control and a control mux for output enable. The part has selective, nonvolatile power-down of unused circuitry. The sense amplifier is optimized for speed and power and is compensated for process, temperature, and pattern variations. The device uses a regulated substrate bias generator optimized for the process to improve latchup immunity and performance

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一种用于组合应用的12ns CMOS可编程逻辑器件

提出了一种采用两层金属、0.8 μm CMOS EPROM技术实现的12ns、400mw可编程逻辑器件。该器件针对组合应用进行了优化，并为锁存、注册或组合输入提供可编程输入宏单元。该器件在28引脚封装中提供1200个等效门，具有13个输入，12个I/ o，一个VCC和两个VSS引脚。除了可编程输入寄存器外，每个I/O引脚都有一个产品项控制的异或门，用于动态输出极性控制，以及用于输出使能的控制mux。该部件具有选择性的、非易失性的未使用电路的断电功能。感应放大器优化了速度和功率，并补偿了工艺，温度和模式变化。该器件使用了针对该工艺优化的可调节衬底偏压发生器，以提高闭锁抗扰度和性能

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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