{"title":"A 318 nA quiescent current 0–10mA output transient enhanced low-dropout regulator applied in energy harvest system","authors":"Hongguang Zhang, Zhangwen Tang","doi":"10.1109/ICAM.2017.8242156","DOIUrl":null,"url":null,"abstract":"A low quiescent current low-dropout regulator (LDO) applied in energy harvest system is presented in this paper. With super-source follower, the LDO has only one pole within loop unity gain bandwidth. And current buffer compensation is utilized to maintain the phase margin under the full range of load current. In order to decrease the power dissipation on the resistors of voltage divider, the resistors are replaced by diode connected PMOSs. The LDO has been designed in TSMC 0.18 μm CMOS 1P8M process with area of 0.011 um2, post-simulation results show that the proposed LDO dissipates 318 nA at zero load, and the LDO can deliver 0–10mA current to load. The overshoot voltage is 3% of output voltage and the recovery time is 12us when load current is changed from 10mA to 0mA.","PeriodicalId":117801,"journal":{"name":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAM.2017.8242156","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A low quiescent current low-dropout regulator (LDO) applied in energy harvest system is presented in this paper. With super-source follower, the LDO has only one pole within loop unity gain bandwidth. And current buffer compensation is utilized to maintain the phase margin under the full range of load current. In order to decrease the power dissipation on the resistors of voltage divider, the resistors are replaced by diode connected PMOSs. The LDO has been designed in TSMC 0.18 μm CMOS 1P8M process with area of 0.011 um2, post-simulation results show that the proposed LDO dissipates 318 nA at zero load, and the LDO can deliver 0–10mA current to load. The overshoot voltage is 3% of output voltage and the recovery time is 12us when load current is changed from 10mA to 0mA.
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