An efficiently checkable subset of TCTL for formal verification of transition systems with delays

Abstract

Model checking transition systems with delays using timed logics such as TCTL is an attractive technique for proper verification of hardware descriptions. TCTL model checking requires the construction of time regions which depends not only on the timed graph, but also the TCTL formula. This limits the efficiency of a pure top-down approach for model checking. We propose a restricted version of TCTL, namely DCTL, which can be checked in a pure top-down manner without augmenting the region graph a priori.