Common-drain CMOS power amplifier: An alternative power amplifier

Abstract

In this paper, we present an 880 MHz common-drain power amplifier (CDPA) in 130 nm CMOS technology. New PA topologies are required to address the issues of linearity, reliability, and efficiency. The CDPA is one such promising topology. Owing to the inherent feedback nature of a CDPA, the output voltage is a replica of input voltage, thus making the CDPA a highly linear amplifier with good efficiency. Secondly, the voltage following property results in significant reduction of the voltage-stress at the device input and output terminals. Small-signal measurement results show a gain of 10.5 dB with Sn less than −10 dB. Large-signal measurement results indicate that the designed CDPA achieves an output 1-dB compression point of 27.9 dBm with an associated 1-dB power added efficiency of 31.9 %. The amplifier saturates at 28.5dBm. The total die area of the amplifier is 0.76 mm 2 including pads. The amplifier is tested at compression point for a duration of 10 hours with average deviation of 0.15 dB in gain, thus indicating a reliable operation.