Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
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引用次数: 2
Abstract
This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52 Mb/s and 5.26 Mb/s data rates respectively. The memory access is reduced by the input caching scheme. And the system complexity is lowered by the efficient interleaver design. This chip is fabricated in a 0.18 /spl mu/m six-metal standard CMOS process, and the measured power dissipation is 83 mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.
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