{"title":"A 2 ns 16 K ECL RAM with reduced word line voltage swing","authors":"Y. Nakase, T. Ikeda, K. Mashiko, S. Kayano","doi":"10.1109/VLSIC.1990.111088","DOIUrl":null,"url":null,"abstract":"A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111088","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation
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