Test circuits to characterize setup/hold/access times, minimum voltage and maximum frequency of operation for memory compilers

Abstract

This paper will explain the design methodology to accurately measure the setup/hold/access time/Vmin & Fmax of memories on silicon. This architecture scheme implements the high resolution fine-tune delays of a few pico-seconds along with the coarse step sizes of ten's to hundreds of pico-seconds depending on technology, along with BIST for memory Vmin & Fmax characterization. This architecture has been implemented on one of our test-chip and silicon measurements show that measured parameters results are within 10% range of the simulated values. Implemented design scheme also ensures the serial as well as parallel measurement of these parameters of the memory instances in order to save the expensive tester time.