An Adaptable 6.4 - 32 GS/s Track-and-Hold Amplifier with Track-Mode Masking for High Signal Power Applications in 55 nm SiGe-BiCMOS

Abstract

This paper presents a track-and-hold amplifier based on a switched emitter follower with demonstrated sampling rates from 6.4 GS/s to 32 GS/s and an analog bandwidth of up to 19 GHz in the hold-mode. Linearity measurements in the first Nyquist zone show 4.9 - 7.9 bits of accuracy for the highest sampling rate, more than 6 bits for up to 25.6 GS/s, more than 7 bits for up to 12.8 GS/s and a maximum of 8.9 bits at 6.4 GS/s, all calculated from the SNDR values. Most comparable circuits use only the THD value to calculate ENOBs, since achieving high SNR is difficult for low signal power circuits. The measurement results of the proposed track-and-hold amplifier were obtained at a high differential input voltage swing of 2.0 Vpp while they can reach even higher values at 1.0 Vpp. The 1-dB compression point is even higher, at 18.9 dBm. This makes the circuit suitable for high signal or noise power applications that demand high data rates and high linearity at the same time, including radio frequency instrumentation and receivers in radar and satellite communications. Designed as the front-end of a folding ADC, an additional benefit is the track-mode masking, recovering the common-mode level of the outputs during the input track-mode, which can be important when working with high input voltages. The third-order intercept point of 27.4 dBm at 25.6 GS/s and up to 34.7 dBm at 6.4 GS/s shows the unique combination of high signal power and high linearity in a sampling circuit above 10 GHz. This is made possible by the modern 55 nm SiGe-BiCMOS technology with high-performance HBTs.