{"title":"A VHSIC compatible CMOS/SOS cell family","authors":"M. J. Fresnadillo Martínez, R. W. Polkinghorn","doi":"10.1109/SOI.1988.95441","DOIUrl":null,"url":null,"abstract":"Summary form only given, as follows. The authors report on a family of standard cells and macro/compilers designed into a VHSIC-compatible, radiation-hard CMOS/SOS (silicon-on-sapphire) process. The family currently consists of one hundred standard cells and five macro/compilers. Standard cells include basic gate and flip-flop functions. The macro/compilers are available for RAMs, ROMs, multipliers, register files, and barrel shifters. A front-end design library is available for these functions on Daisy workstations to permit schematic capture, logic simulation, timing analysis, and netlist generation. Automatic placement and route is accomplished using VLSI Technology Inc. software on Apollo workstations. Compiled functions use VLSI technology compiler software. Back annotation to the Daisy permits resimulation using exact routing capacitances.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"160 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. SOS/SOI Technology Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.1988.95441","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Summary form only given, as follows. The authors report on a family of standard cells and macro/compilers designed into a VHSIC-compatible, radiation-hard CMOS/SOS (silicon-on-sapphire) process. The family currently consists of one hundred standard cells and five macro/compilers. Standard cells include basic gate and flip-flop functions. The macro/compilers are available for RAMs, ROMs, multipliers, register files, and barrel shifters. A front-end design library is available for these functions on Daisy workstations to permit schematic capture, logic simulation, timing analysis, and netlist generation. Automatic placement and route is accomplished using VLSI Technology Inc. software on Apollo workstations. Compiled functions use VLSI technology compiler software. Back annotation to the Daisy permits resimulation using exact routing capacitances.<>