The photocurrent from ultrafast photoconductive switches formed on SOS and SIMOX (separation by implantation of oxygen) wafers with microstrip transmission line technology has been measured. Some of these switches exhibit nonlinear response as a function of applied electrical bias and incident optical power. The nature of the observed behavior is critically dependent on the order of ion implantation and metallization processing steps during the fabrication procedure. Device characteristics are also dependent on the extent of damage induced by ion-implantation. Ion-implantation conditions were based on present models of metal-semiconductor contacts to optimize either linear or nonlinear photoconductive response of these switches. Beam currents were limited to 0.22 mu A/cm/sup 2/ to limit the maximum wafer temperature during ion implantation to <60 degrees C. Depth profiles of ion-implantation-induced damage were modeled using the TRIM-88 Monte Carlo calculation. Simulations of the vacancy and interstitial concentration as a function of depth were obtained both for single energy implants and the sum of multiple energy implants in SIMOX and SOS at various dosages. After implantation, damage-versus-depth profiles were measured with Rutherford backscattering spectroscopy, yielding a comparison of the state of amorphization and in situ recrystallization.<>
{"title":"SOS/SOI optoelectronic switches: effects of ion-implantation and materials processing on nonlinear photoconductive response","authors":"J. Knudsen, D.D. Smith, S. Moss","doi":"10.1109/SOI.1988.95407","DOIUrl":"https://doi.org/10.1109/SOI.1988.95407","url":null,"abstract":"The photocurrent from ultrafast photoconductive switches formed on SOS and SIMOX (separation by implantation of oxygen) wafers with microstrip transmission line technology has been measured. Some of these switches exhibit nonlinear response as a function of applied electrical bias and incident optical power. The nature of the observed behavior is critically dependent on the order of ion implantation and metallization processing steps during the fabrication procedure. Device characteristics are also dependent on the extent of damage induced by ion-implantation. Ion-implantation conditions were based on present models of metal-semiconductor contacts to optimize either linear or nonlinear photoconductive response of these switches. Beam currents were limited to 0.22 mu A/cm/sup 2/ to limit the maximum wafer temperature during ion implantation to <60 degrees C. Depth profiles of ion-implantation-induced damage were modeled using the TRIM-88 Monte Carlo calculation. Simulations of the vacancy and interstitial concentration as a function of depth were obtained both for single energy implants and the sum of multiple energy implants in SIMOX and SOS at various dosages. After implantation, damage-versus-depth profiles were measured with Rutherford backscattering spectroscopy, yielding a comparison of the state of amorphization and in situ recrystallization.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The two bonding substances investigated were BPSG TEOS and PSG glasses used in semiconductor manufacturing. Both substances can be deposited in an LPCVD furnace on either bare silicon or wafers covered by previously grown thermal oxides. BPSG TEOS (3% phosphorous, 3% boron) softens at 850 degrees C, and usable bonded wafers were achieved by bonding wafers at 950 degrees C, in oxygen or nitrogen, using a ramp-up/ramp-down procedure. PSG, formed by the reduction of POCl/sub 3/ gas, softens at a temperature of 900 degrees C, and usable bonded wafers were achieved by bonding wafers at 950 degrees C using times as short as one hour (no shorter times were tried). Wafers were assembled for bonding within 24 hours of deposition to avoid the creation of circular nonbonded areas caused by outgassing of moisture or dopant in the film. Spin on glass could be used to alleviate the outgassing problem, but in that case the minimum bonding temperature increases to 1100 degrees C. Bond quality was evaluated by destructive wafer separation and physical inspection of the bonded oxide and by grinding back the bonded wafer and assessing the strength of the bond with sonic treatment. Heat stressing was used to determine whether BPSG TEOS could be used to make bonded wafers capable of withstanding the rigors of the standard manufacturing process line. Bond reliability, dopant diffusion, induced bow, and wafer crystal slip were measured on bonded wafers.<>
{"title":"Wafer bonding using low temperature melting glass","authors":"J. M. Mcnamara, J. Raby","doi":"10.1109/SOI.1988.95390","DOIUrl":"https://doi.org/10.1109/SOI.1988.95390","url":null,"abstract":"Summary form only given. The two bonding substances investigated were BPSG TEOS and PSG glasses used in semiconductor manufacturing. Both substances can be deposited in an LPCVD furnace on either bare silicon or wafers covered by previously grown thermal oxides. BPSG TEOS (3% phosphorous, 3% boron) softens at 850 degrees C, and usable bonded wafers were achieved by bonding wafers at 950 degrees C, in oxygen or nitrogen, using a ramp-up/ramp-down procedure. PSG, formed by the reduction of POCl/sub 3/ gas, softens at a temperature of 900 degrees C, and usable bonded wafers were achieved by bonding wafers at 950 degrees C using times as short as one hour (no shorter times were tried). Wafers were assembled for bonding within 24 hours of deposition to avoid the creation of circular nonbonded areas caused by outgassing of moisture or dopant in the film. Spin on glass could be used to alleviate the outgassing problem, but in that case the minimum bonding temperature increases to 1100 degrees C. Bond quality was evaluated by destructive wafer separation and physical inspection of the bonded oxide and by grinding back the bonded wafer and assessing the strength of the bond with sonic treatment. Heat stressing was used to determine whether BPSG TEOS could be used to make bonded wafers capable of withstanding the rigors of the standard manufacturing process line. Bond reliability, dopant diffusion, induced bow, and wafer crystal slip were measured on bonded wafers.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129052426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Papaioannou, V. Ioannou-Sugleridis, S. Cristoloveanu, M. Bruel, P. Hemment
Minority carrier trapping in unprocessed SOI materials has been studied by photoinduced transient current spectroscopy (PTCS). The method consists of filling interface states and bulk traps by means of pulsed photoexcitation and then monitoring the transient current that corresponds to the carrier emission process. The experiment was carried out in SIMOX (separation by implanted oxygen) material synthesized by deep oxygen implantation and high-temperature annealing. The illumination was provided by a light-emitting diode array. The sample was biased at 0.2 V, and the current was monitored using a measured system composed of a current-to-voltage converter and a lock-in amplifier. The output voltage is related to the density of traps while the frequency gives their emission rate and energy position in the gap. A typical energy profile is shown, which demonstrates a clear increase of the trap density near the valence band edge. The density of 10/sup 12/ traps/cm/sup 2/ is a reasonable value as far as the proximity of the buried interface is concerned and should not significantly affect the performance of integrated circuits. PTCS experiments have been conducted in parallel with conventional static photoconductivity and photo Hall effect. A donorlike process-induced contamination was found to occur due to the oxygen activation of annealing conditions. The region situated near the buried interface is shown to be responsible for the transition to hopping conduction mechanism below 60 K. A two-band model accounts for the minimum observed in the carrier concentration curve.<>
{"title":"Investigation of trapping properties in SIMOX films by photo-induced transient current spectroscopy","authors":"G. Papaioannou, V. Ioannou-Sugleridis, S. Cristoloveanu, M. Bruel, P. Hemment","doi":"10.1109/SOI.1988.95398","DOIUrl":"https://doi.org/10.1109/SOI.1988.95398","url":null,"abstract":"Minority carrier trapping in unprocessed SOI materials has been studied by photoinduced transient current spectroscopy (PTCS). The method consists of filling interface states and bulk traps by means of pulsed photoexcitation and then monitoring the transient current that corresponds to the carrier emission process. The experiment was carried out in SIMOX (separation by implanted oxygen) material synthesized by deep oxygen implantation and high-temperature annealing. The illumination was provided by a light-emitting diode array. The sample was biased at 0.2 V, and the current was monitored using a measured system composed of a current-to-voltage converter and a lock-in amplifier. The output voltage is related to the density of traps while the frequency gives their emission rate and energy position in the gap. A typical energy profile is shown, which demonstrates a clear increase of the trap density near the valence band edge. The density of 10/sup 12/ traps/cm/sup 2/ is a reasonable value as far as the proximity of the buried interface is concerned and should not significantly affect the performance of integrated circuits. PTCS experiments have been conducted in parallel with conventional static photoconductivity and photo Hall effect. A donorlike process-induced contamination was found to occur due to the oxygen activation of annealing conditions. The region situated near the buried interface is shown to be responsible for the transition to hopping conduction mechanism below 60 K. A two-band model accounts for the minimum observed in the carrier concentration curve.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123629035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An MOS transistor formed partly on lateral epitaxial silicon film on insulator (called the TOLE structure) has been proposed and applied to a DRAM cell. The authors have investigated the potential of the CMOS-TOLE structure for application to future ultra-large-scale integrated circuits (ULSIs). The test CMOS-TOLEs had a 400-nm-thick SiO/sub 2/ film for the SOI insulator, a 100 approximately 200-nm-thick silicon film, and a 20-nm-thick gate oxide. The designed channel width and length for the CMOS-TOLEs measured were 20/2 approximately 2.5 and 6/2 mu m. The bulk part length was 1.2 mu m. The advantages and properties of the structure are discussed. It has been estimated that the necessary storage charge for the CMOS-TOLE DRAM is about 40% of that for the bulk CMOS DRAM and that the typical logic gate delay for the CMOS-TOLE is about 60% of that for the bulk CMOS. Parasitic sidewall channel formation, which is a problem for the n-channel TOLE due to its isolation structure, has been suppressed by channel side impurity control. The leakage current level has been reduced to a value approximately ten times larger than that for the conventional bulk junction.<>
{"title":"A CMOS/partial-SOI structure for future ULSIs","authors":"K. Terada, T. Ishijima, T. Kubota, M. Sakao","doi":"10.1109/SOI.1988.95411","DOIUrl":"https://doi.org/10.1109/SOI.1988.95411","url":null,"abstract":"An MOS transistor formed partly on lateral epitaxial silicon film on insulator (called the TOLE structure) has been proposed and applied to a DRAM cell. The authors have investigated the potential of the CMOS-TOLE structure for application to future ultra-large-scale integrated circuits (ULSIs). The test CMOS-TOLEs had a 400-nm-thick SiO/sub 2/ film for the SOI insulator, a 100 approximately 200-nm-thick silicon film, and a 20-nm-thick gate oxide. The designed channel width and length for the CMOS-TOLEs measured were 20/2 approximately 2.5 and 6/2 mu m. The bulk part length was 1.2 mu m. The advantages and properties of the structure are discussed. It has been estimated that the necessary storage charge for the CMOS-TOLE DRAM is about 40% of that for the bulk CMOS DRAM and that the typical logic gate delay for the CMOS-TOLE is about 60% of that for the bulk CMOS. Parasitic sidewall channel formation, which is a problem for the n-channel TOLE due to its isolation structure, has been suppressed by channel side impurity control. The leakage current level has been reduced to a value approximately ten times larger than that for the conventional bulk junction.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130201822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The bonding process and mechanism and the electrical and material properties of the Si on SiO/sub 2/ substrate produced by two-step thermal bonding technology are described. Experimental results on the relation between fracture strength and treatment temperature are reported. They show that the bonding process consists of two main steps. The first step is a low-temperature initial bonding process in which polymerization of silanol bonds occurs. The second step is a high-temperature process (900-1250 degrees C) in which the mutual-diffusion process acts as the primary means of grain boundary rearrangement and void elimination. The mating surface contact area grows to a large fraction of bonding area, which increases the fracture strength greatly. The experiments show that the process can be applied to other semiconductors and insulators, such as GaAs, quartz, and silicon nitride.<>
介绍了采用两步热键合技术制备的Si on SiO/ sub2 /基板的键合工艺、键合机理、电学性能和材料性能。报道了断裂强度与处理温度关系的实验结果。它们表明，键合过程包括两个主要步骤。第一步是低温初始键合过程，其中硅烷醇键发生聚合。第二步是高温过程(900-1250℃)，其中相互扩散过程是晶界重排和空洞消除的主要手段。配合面接触面积增大到结合面积的很大一部分，大大提高了断裂强度。实验表明，该工艺可以应用于其他半导体和绝缘体，如砷化镓、石英和氮化硅。
{"title":"Silicon on SiO/sub 2/ by two step thermal bonding (TSTB) process","authors":"Xu Xiao-li, Zhan Juan, Tong Qin-yi","doi":"10.1109/SOI.1988.95406","DOIUrl":"https://doi.org/10.1109/SOI.1988.95406","url":null,"abstract":"The bonding process and mechanism and the electrical and material properties of the Si on SiO/sub 2/ substrate produced by two-step thermal bonding technology are described. Experimental results on the relation between fracture strength and treatment temperature are reported. They show that the bonding process consists of two main steps. The first step is a low-temperature initial bonding process in which polymerization of silanol bonds occurs. The second step is a high-temperature process (900-1250 degrees C) in which the mutual-diffusion process acts as the primary means of grain boundary rearrangement and void elimination. The mating surface contact area grows to a large fraction of bonding area, which increases the fracture strength greatly. The experiments show that the process can be applied to other semiconductors and insulators, such as GaAs, quartz, and silicon nitride.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114557284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Reedy, M. Burgener, S. R. Clayton, O. Csanadi, W. Dubbelday, G. Garcia, B. Offord
Summary form only given, as follows. HIgh-performance circuitry has been designed, simulated, fabricated, and tested in 100-nm thick double-solid-phase-epitaxy SOS. The source and drain regions outside the oxide sidewall spacers were silicided to the sapphire substrate, thereby providing self-aligned contacts to the transistors as well as an additional level of interconnects. The n/sup +/ and p/sup +/ regions under the oxide sidewalls serve as the actual source and drain regions. Ring oscillators with a 1.25- mu m gate length exhibit 120-ps gate delays, which compare well to simulation results of 125 ps. Simulations of electron-beam-written 0.5- mu m-gate-length ring oscillators predict gate delays of about 40 ps.<>
{"title":"High performance CMOS in silicide to sapphire (CMOS/STS)","authors":"R. Reedy, M. Burgener, S. R. Clayton, O. Csanadi, W. Dubbelday, G. Garcia, B. Offord","doi":"10.1109/SOI.1988.95442","DOIUrl":"https://doi.org/10.1109/SOI.1988.95442","url":null,"abstract":"Summary form only given, as follows. HIgh-performance circuitry has been designed, simulated, fabricated, and tested in 100-nm thick double-solid-phase-epitaxy SOS. The source and drain regions outside the oxide sidewall spacers were silicided to the sapphire substrate, thereby providing self-aligned contacts to the transistors as well as an additional level of interconnects. The n/sup +/ and p/sup +/ regions under the oxide sidewalls serve as the actual source and drain regions. Ring oscillators with a 1.25- mu m gate length exhibit 120-ps gate delays, which compare well to simulation results of 125 ps. Simulations of electron-beam-written 0.5- mu m-gate-length ring oscillators predict gate delays of about 40 ps.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123393912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An implant-through-contact (ITC) scheme to fabricate offset-gate high-voltage (HV) thin-film transistors (TFTs) has recently been proposed. The ITC scheme saves the n/sup +/ mask required in the conventional methods by performing the n/sup +/ source-drain implant only after contact opening. The device performances of ITC and conventional HV transistors has been fully characterized and compared. Both ITC and conventional HV TFTs have been fabricated on the same wafers by making the ITC TFTs during the conventional n/sup +/ source-drain implant and applying another n/sup +/ implant after contact opening for forming their source-drain. Experimental results show that ITC transistors have a higher breakdown voltage. ITC transistors also show better alignment tolerance in regard to the drain offset length, which is beneficial for large area applications. The observed improvements are ascribed to the existence of a drain metal field plate overlapping the offset region of ITC TFTs. The drain metal pad serves to accumulate and enhance carriers along the offset region, thus minimizing its sensitivity to the length. This has been confirmed by fabricating conventional HV TFTs with and without the drain overlapping field plate.<>
{"title":"Comparisons of implant-through-contact and conventional high-voltage TFTs","authors":"T. Huang, A. Lewis, A. Chiang, I. Wu, R. Bruce","doi":"10.1109/SOI.1988.95412","DOIUrl":"https://doi.org/10.1109/SOI.1988.95412","url":null,"abstract":"An implant-through-contact (ITC) scheme to fabricate offset-gate high-voltage (HV) thin-film transistors (TFTs) has recently been proposed. The ITC scheme saves the n/sup +/ mask required in the conventional methods by performing the n/sup +/ source-drain implant only after contact opening. The device performances of ITC and conventional HV transistors has been fully characterized and compared. Both ITC and conventional HV TFTs have been fabricated on the same wafers by making the ITC TFTs during the conventional n/sup +/ source-drain implant and applying another n/sup +/ implant after contact opening for forming their source-drain. Experimental results show that ITC transistors have a higher breakdown voltage. ITC transistors also show better alignment tolerance in regard to the drain offset length, which is beneficial for large area applications. The observed improvements are ascribed to the existence of a drain metal field plate overlapping the offset region of ITC TFTs. The drain metal pad serves to accumulate and enhance carriers along the offset region, thus minimizing its sensitivity to the length. This has been confirmed by fabricating conventional HV TFTs with and without the drain overlapping field plate.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131731452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Zavracky, D. Vu, L. Allen, W. Henderson, M. Batty, T. E. Jersey
Summary form only given. High-quality SOI layers have been produced using isolated silicon epitaxy (ISE) technology, which is based on lateral epitaxy by seeded solidification (LESS) and zone melting recrystallization (ZMR). ISE wafers are manufactured in production volumes and have consistently demonstrated low-defect density (<10/sup 6//cm/sup 2/), high-quality surfaces (haze less than 2000 p.p.m.), no protrusions, and low warpage (less than 80 mu m). Single-crystal silicon films have been obtained with excellent crystalline properties as compared to other SOI techniques. ISE wafers have no large grain boundaries or subboundaries. Low densities of isolated threading dislocations with occasional defect clusters have been observed. The high quality of the interface between the oxide and silicon thin film and the interface between the oxide and the substrate has been demonstrated. Electrical characterization of ISE films indicates low background dopant density (<10/sup 15//cm/sup 3/) and low oxide charge density at the Si-film-buried oxide interface (<10/sup 11//cm/sup 2/). These measurements were performed on depletion-mode MOS transistors. Channel leakage currents were less than 0.1 pA/ mu m on enhancement-mode MOS transistors made using a mesa technique. Carrier mobilities were near bulk values. In lateral pn diodes, the junction leakage was less than 0.3 mu A/cm/sup 2/ with a 5-V reverse bias applied. DLTS measurements showed no detectable levels of electrically active traps.<>
{"title":"High quality SOI material produced using isolated silicon epitaxy","authors":"P. Zavracky, D. Vu, L. Allen, W. Henderson, M. Batty, T. E. Jersey","doi":"10.1109/SOI.1988.95397","DOIUrl":"https://doi.org/10.1109/SOI.1988.95397","url":null,"abstract":"Summary form only given. High-quality SOI layers have been produced using isolated silicon epitaxy (ISE) technology, which is based on lateral epitaxy by seeded solidification (LESS) and zone melting recrystallization (ZMR). ISE wafers are manufactured in production volumes and have consistently demonstrated low-defect density (<10/sup 6//cm/sup 2/), high-quality surfaces (haze less than 2000 p.p.m.), no protrusions, and low warpage (less than 80 mu m). Single-crystal silicon films have been obtained with excellent crystalline properties as compared to other SOI techniques. ISE wafers have no large grain boundaries or subboundaries. Low densities of isolated threading dislocations with occasional defect clusters have been observed. The high quality of the interface between the oxide and silicon thin film and the interface between the oxide and the substrate has been demonstrated. Electrical characterization of ISE films indicates low background dopant density (<10/sup 15//cm/sup 3/) and low oxide charge density at the Si-film-buried oxide interface (<10/sup 11//cm/sup 2/). These measurements were performed on depletion-mode MOS transistors. Channel leakage currents were less than 0.1 pA/ mu m on enhancement-mode MOS transistors made using a mesa technique. Carrier mobilities were near bulk values. In lateral pn diodes, the junction leakage was less than 0.3 mu A/cm/sup 2/ with a 5-V reverse bias applied. DLTS measurements showed no detectable levels of electrically active traps.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122579902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. The authors have investigated secondary ion mass spectrometry (SIMS) relative sensitivity factors, detection limits, and interferences for the detection and determination of the densities of various impurities in SOI wafers (H, C, N O, Na, Al, K, Ti Ti, Cr, Mn Fe, and Cu) using both oxygen and Cs SIMS, with both positive and negative spectrometry. They have used implantation studies of rare isotopes as well as common isotopes and high mass resolution SIMS to sort out interference issues and to determine detection limits. Ion yields and relative sputtering rates were determined in the Si and SIO/sub 2/ SOI layers. More than 60 SOI structures, including devices, from various sources and annealed at various temperatures have been examined. The gettering action of C, P, and Ge ion implantation into SIMOX wafers, subsequently annealed at 1300 or 1350 degrees C), has also been studied. Significant redistribution (gettering) of Cu into the implanted region has been observed.<>
只提供摘要形式。作者研究了二次离子质谱法(SIMS)的相对灵敏度因素，检测限和干扰，用于检测和测定SOI晶圆中各种杂质(H, C, N O, Na, Al, K, Ti Ti, Cr, Mn Fe和Cu)的密度，使用氧和Cs SIMS，正负光谱法。他们利用稀有同位素和常见同位素的植入研究以及高质量分辨率SIMS来整理干扰问题并确定检测限。测定了Si层和SIO/ sub2 / SOI层的离子产率和相对溅射速率。60多个SOI结构，包括器件，从不同的来源和退火在不同的温度进行了研究。C、P和Ge离子注入SIMOX晶圆后，在1300或1350℃下退火，其捕集作用也被研究。观察到铜在植入区有明显的再分布(吸收)。
{"title":"Identification and reduction of impurities in SOI wafers using secondary ion mass spectrometry and implantation-induced gettering","authors":"R. Wilson, P. Vasudev","doi":"10.1109/SOI.1988.95423","DOIUrl":"https://doi.org/10.1109/SOI.1988.95423","url":null,"abstract":"Summary form only given. The authors have investigated secondary ion mass spectrometry (SIMS) relative sensitivity factors, detection limits, and interferences for the detection and determination of the densities of various impurities in SOI wafers (H, C, N O, Na, Al, K, Ti Ti, Cr, Mn Fe, and Cu) using both oxygen and Cs SIMS, with both positive and negative spectrometry. They have used implantation studies of rare isotopes as well as common isotopes and high mass resolution SIMS to sort out interference issues and to determine detection limits. Ion yields and relative sputtering rates were determined in the Si and SIO/sub 2/ SOI layers. More than 60 SOI structures, including devices, from various sources and annealed at various temperatures have been examined. The gettering action of C, P, and Ge ion implantation into SIMOX wafers, subsequently annealed at 1300 or 1350 degrees C), has also been studied. Significant redistribution (gettering) of Cu into the implanted region has been observed.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133944177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Sundaresan, M. Matloubian, C. Chen, W. Bailey, B. Mao, T. Blake, A. Peterson, G. Pollack
Summary form only given. Separation by implantation of oxygen (SIMOX) into silicon to obtain silicon-on-insulator substrates has emerged as the leading technology for radiation-hard integrated circuits. A key issue in building CMOS devices on SIMOX substrates is the device leaking current, which in turn determines the standby current of circuits. One cause of high leakage current is metal impurities incorporated during the oxygen implant. A second mechanism for leakage current in mesa-isolated SIMOX transistors is identified here. This current, which occurs along mesa edges, is more detrimental to circuit performance. It is random, and the probability of its occurrence increases with an increase in the number of edges, shorter-channel transistors, and/or longer source-drain anneal cycles. Measurements suggest that the random edge leakage is caused by enhanced lateral diffusion of source-drain dopants along the mesa edges.<>
{"title":"Identification and control of edge leakage in mesa-isolated SIMOX MOSFETs","authors":"R. Sundaresan, M. Matloubian, C. Chen, W. Bailey, B. Mao, T. Blake, A. Peterson, G. Pollack","doi":"10.1109/SOI.1988.95450","DOIUrl":"https://doi.org/10.1109/SOI.1988.95450","url":null,"abstract":"Summary form only given. Separation by implantation of oxygen (SIMOX) into silicon to obtain silicon-on-insulator substrates has emerged as the leading technology for radiation-hard integrated circuits. A key issue in building CMOS devices on SIMOX substrates is the device leaking current, which in turn determines the standby current of circuits. One cause of high leakage current is metal impurities incorporated during the oxygen implant. A second mechanism for leakage current in mesa-isolated SIMOX transistors is identified here. This current, which occurs along mesa edges, is more detrimental to circuit performance. It is random, and the probability of its occurrence increases with an increase in the number of edges, shorter-channel transistors, and/or longer source-drain anneal cycles. Measurements suggest that the random edge leakage is caused by enhanced lateral diffusion of source-drain dopants along the mesa edges.<<ETX>>","PeriodicalId":391934,"journal":{"name":"Proceedings. SOS/SOI Technology Workshop","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134439142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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