{"title":"A Novel Low-temperature Gate Oxynitride For CMOS Technologies","authors":"Diaz, Cox, Greene, Perlaki, Carr, Manna, Bayoumi, Cao, Shamma, Tavassoli, Chi, Farrar, Lefforge, Chang, Langley, Marcoux","doi":"10.1109/VLSIT.1997.623689","DOIUrl":null,"url":null,"abstract":"A new-low temperature gate oxynitride has been developed for sub-0.25 pm CMOS technologies. In this process, nitrous oxide is cracked in a pre-furnace at high tem- perature to generate nitric oxide that flows into the main fur- nace where the gate oxidation is carried out at low tempera- ture. Physical analysis and gate oxide integrity data are used to demonstrate effective nitridation of the gate oxides grown in this fashion. The process was successfully integrated into a 0.15 pm, 1.5 V CMOS technology with 25 A physical gate oxide to minimize short channel effects and improve device performance and hot carrier reliability.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A new-low temperature gate oxynitride has been developed for sub-0.25 pm CMOS technologies. In this process, nitrous oxide is cracked in a pre-furnace at high tem- perature to generate nitric oxide that flows into the main fur- nace where the gate oxidation is carried out at low tempera- ture. Physical analysis and gate oxide integrity data are used to demonstrate effective nitridation of the gate oxides grown in this fashion. The process was successfully integrated into a 0.15 pm, 1.5 V CMOS technology with 25 A physical gate oxide to minimize short channel effects and improve device performance and hot carrier reliability.
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