{"title":"Soft error immunity of 1-Volt CMOS memory cells with MTCMOS technology","authors":"T. Douseki, S. Mutoh, T. Ueki, J. Yamada","doi":"10.1109/ICMTS.1995.513955","DOIUrl":null,"url":null,"abstract":"Soft error immunity of a 1-V operating CMOS memory cell is described. A test chip using multi threshold CMOS (MTCMOS) technology is fabricated and the immunity of the memory cell is evaluated. It is demonstrated that a full CMOS memory cell has high immunity at 1-V operation.","PeriodicalId":432935,"journal":{"name":"Proceedings International Conference on Microelectronic Test Structures","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.1995.513955","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Soft error immunity of a 1-V operating CMOS memory cell is described. A test chip using multi threshold CMOS (MTCMOS) technology is fabricated and the immunity of the memory cell is evaluated. It is demonstrated that a full CMOS memory cell has high immunity at 1-V operation.
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