Behavioral synthesis technique for flexible IP's communications

Abstract

Among factors limiting the reuse of intellectual property (IPs) blocks into wide range of systems on chips (SoCs) is the inflexibility of their communication protocols. This paper presents an approach for designing IP blocks with relaxed timing constraints to exchange data with various environments. The approach is based on decoupling computation from communication and on an adequate scheduling of operations during the high level synthesis of computation units. Experimentations performed on the MPEG4 intraprediction IP block show the efficiency of our solution