High-level modeling and testing of multiple control faults in digital systems

Abstract

A new method for high level fault modeling to improve the test generation for the control parts of digital systems was proposed. We developed a new high-level functional fault model based on High-Level Decision Diagrams (HLDD). It allows uniform handling of possible defects in different control functions related to instruction decoding, data addressing, and data manipulation. It was shown how the proposed high-level fault model can be mapped on the low-level faults of a joint class of stuck-at faults (SAF), conditional SAF and bridging faults. We proposed uniform procedures for high-level fault activation as a graph traversing procedure on HLDDs related to selection of control signals, and for fault propagation as a task of solving data constraints without using implementation details. Experimental results demonstrated that combining both, high-level control fault reasoning and low-level test generation for data part of a system can help to achieve higher fault coverage and detection of redundant faults than using low-level test generation approach alone.