Physical verification of microelectronics "mask patterns" with calibre SVRF rule files

Abstract

Microelectronics components are made with different technological steps which uses dedicated masks: for example, the poly mask is used for the polysilicon deposition on the silicon active area. These masks include the design itself and shapes which are called the mask patterns. These features enable a mechanical isolation during the die sawing and a visual check for each technological step. The mask patterns layout generators are developed by the foundry and used during the layout finishing step of the design. The proposed work gives a validation solution using the Calibre SVRF set of rules and the signature approach already introduced for other applications in ST Design Solutions