Plasma doping: production worthy solution for 65nm and beyond technology nodes

Abstract

65nm and beyond advanced logic and DRAM devices will require decreasing junction depths and poly thickness at increasing doses. Present beam-line technology will suffer decreasing throughput during this transition as a result of space charge effects. Plasma doping is a well characterized alternative to beam-line technology that meets the doping requirements for <65nm ITRS technology nodes. This is accomplished at superior throughput levels which are largely energy insensitive. The simplicity of the plasma doping tool design and maturing process control features offer a promising future for production worthiness of this technique. Varian's PLAD tool has demonstrated advanced logic USJ SDE/SD formation as well as advanced DRAM poly and SD doping capability. In this paper we present as-implanted and annealed SIMS profiles to highlight the sub-kV doping capability of the PLAD system for PMOS transistor fabrication and its impact on the R/sub s/ vs. X/sub J/ figure of merit. TEM data will also be presented to show lack of residual damage after a high nominal dose implant which agrees well with low junction leakage observed on PLAD doped devices. The production worthiness of the processes mentioned above is demonstrated with uniformity, repeatability, metals purity and particle performance comparable to that attainable with beam-line implants.