An ESD protection scheme for deep sub-micron ULSI circuits

Abstract

The paper describes a robust scheme for on-chip protection of sub-micron ULSI circuits against ESD stress using a novel (low voltage) zener-triggered SCR, and a zener-triggered thin gate oxide MOSFET. The devices are implemented in state of the art, 3.3 V, 0.5 /spl mu/m feature site dual-poly, full-SALICIDE technology. The trigger and holding voltages of the described ESD protection elements are tunable over wide operating ranges and the devices trigger consistently and predictably at pre-determined values suitable for sub-micron technologies. The effectiveness of this methodology in providing ESD protection up to 15 kV is successfully demonstrated.