A 13-bit 60MS/s split pipelined ADC with background gain and mismatch error calibration

Abstract

This paper proposes acomprehensive background gain and mismatch error calibration technique for split ADC, without injecting any test signal. By employing a comparator threshold random selection method the input/output transfer characteristics of each split ADC channel is different. Based on Least Mean Square (LMS) adaptation the interstage gain error and capacitor mismatch error are corrected. All the estimations and corrections are performed in the digital domain, resulting in slight modifications of the analog circuit. The proposed calibration technique is applied on a 13-bit 60MS/s pipelined ADC. Fabricated in a 90nm CMOS process, the ADC achieves 70.8dB SNDR while consuming 63.8mW. The FoM is 377fJ/step at DC and 452 fJ/step at Nyquist.