A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power Gating

Abstract

Physically Unclonable Functions (PUFs) need error correction whilst regenerating Secret Keys in cryptography. The proposed 8-Transistor (8T) PUF, which coordinates with the power gating technique, can significantly accelerate a single evaluation cycle 1000 times faster than $\mathbf{6}\mathbf{T}$ -SRAM PUF does with a 12.8% area increase. This design enables multiple evaluations even in the key regeneration phase in field, hence greatly reducing the number of errors and the hardware penalty for error correction. The $\mathbf{8T}$ PUF derives from the $\mathbf{6}\mathbf{T}$ SRAM. It is built to eliminate data retention swiftly and maximise physical mismatches. And a two-phase power gating module is designed to provide controllable power-on/off cycles rapidly for the chosen PUF clusters in order to facilitate statistical measurements and curb the in-rush current, thereby enhancing PUF entropy and security. An architecture of the power-gated PUF is developed to accommodate fast multiple evaluations. Post-layout Monte Carlo simulations were performed with Cadence, and the extracted PUF Responses were processed with Matlab to evaluate the 8T PUF performance and statistical metrics for subsequent inclusion into PUF Responses.