High Signal Integrity Transmission Line Using Microchip Capacitors and Inductors

Takahiko Kano, M. Yasunaga
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Abstract

In order to improve signal integrity (SI) in PCB traces, or transmission lines, impedance matching techniques have been widely used so far. However, in the frequency domain of more than 5 GHz, it becomes difficult to make impedance matching designs in printed circuit boards (PCBs). In this paper, we propose a novel trace structure called "Capacitor Inductor Segmental Transmission Line (CL-STL)", in which not impedance matching but "mismatching" is used to improve SI. In the CL-STL, microchip capacitors and inductors are connected to the transmission line to make impedance mismatching points and to generate reflection waves intentionally, and those reflection waves are superposed onto the original distorted wave to get it into shape. In the CL-STL design, we make use of the cuckoo search algorithm, which is one of the swarm intelligence optimization algorithms, to solve the combinatorial explosion problem of microchip capacitors and inductors. We apply the CL-STL to an 8 Gbps PCB trace and obtain a high SI eye-diagram, the height and the width of which are improved by 6.9 and 1.44 times, respectively.
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采用微芯片电容器和电感的高信号完整性传输线
为了提高PCB走线或传输线的信号完整性(SI),阻抗匹配技术迄今已被广泛应用。然而,在大于5ghz的频域,印制电路板(pcb)的阻抗匹配设计变得困难。在本文中,我们提出了一种新的走线结构,称为“电容电感分段传输线(CL-STL)”,其中使用“失配”而不是阻抗匹配来提高SI。在CL-STL中,将微芯片电容和电感连接到传输线上,形成阻抗失配点,并有意产生反射波,将反射波叠加到原畸变波上,使其成形。在CL-STL设计中,我们利用群智能优化算法之一的布谷鸟搜索算法来解决微芯片电容器和电感器的组合爆炸问题。我们将CL-STL应用于8gbps的PCB走线,得到了高SI眼图,其高度和宽度分别提高了6.9倍和1.44倍。
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