ExTest scheduling for 2.5D system-on-chip integrated circuits

Abstract

Interposer-based 2.5D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents an efficient ExTest scheduling strategy that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number of output test pins. We present scheduling and optimization results for a “monster” die with 50 million flip-flops in a 2.5D IC, which is currently in production, to highlight the effectiveness of the proposed test strategy.