Appraisal of BiCMOS from circuit voltage and delay time

Abstract

The authors present a general appraisal of voltage-dependent speed degradation for three kinds of BiCMOS logic circuits from the viewpoints of (1) essential delays without parasitic capacitances, (2) practical delays with parasitics, (3) full-swing (power to ground) mode operation, and (4) partial-swing operation. The essential delay times of the three circuits are analytically derived and effects of parasitic capacitances are discussed. The degradation of delay time is shown to depend significantly on whether the input signal swings fully or partially. For partial-swing operation, it has been found that an emitter follower circuit with bias diodes is effective. In general, full-swing operation can be achieved by inserting resistors