M. Yotsuyanagi, A. Yukawa, K. Hino-oka, K. Shiraki, H. Abiko
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引用次数: 4
Abstract
A 12-bit 5-μs CMOS analog-to-digital converter (ADC) has been realized in a 4-mm2 area with power consumption of only 25 mW ADC with 25 mW at a supply voltage of 5 V. Trimming and software calibration were not used. A four-step recursive subranging architecture has been adopted
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