Sudhanshu Khanna, Steven Bartling, M. Clinton, S. Summerfelt, John A. Rodriguez, H. McAdams
{"title":"Zero leakage microcontroller with 384ns wakeup time using FRAM mini-array architecture","authors":"Sudhanshu Khanna, Steven Bartling, M. Clinton, S. Summerfelt, John A. Rodriguez, H. McAdams","doi":"10.1109/ASSCC.2013.6690972","DOIUrl":null,"url":null,"abstract":"Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6690972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Catalog ULP microcontrollers (MCUs) have to balance the needs of diverse customers by providing high performance along with near zero standby power and fast wakeup times for real time applications. We present a full HVT 8MHz 75uA/MHz Non-Volatile Logic (NVL) based MCU that has zero standby power and an ultrafast 384ns wakeup time. Non-volatile mini-arrays distributed throughout the logic domain of the MCU snapshot the state of all sequential elements before the MCU goes into a power gated standby mode. Upon wakeup no bootup is required. A high bandwidth parallel connection between the flipflops and mini-arrays helps achieve fast MCU wakeup. NVL has no impact on MCU active mode performance and power and adds only 3.6% to the SoC area. By eliminating leakage in standby mode, NVL allows use of high performance leaky processes in MCU design. We present results from a second generation full SVT 32MHz NVL MCU. The SVT SoC has 4x higher active mode performance or 30% lower active energy than the HVT SoC, but can still achieve zero leakage using NVL.