Design Optimization and Automation for Secure Cryptographic Circuits

Abstract

Various logic design styles have been proposed to counteract DPA (Differential Power Analysis) attacks for secure cryptographic IC design. However, only a couple of papers addressed the automatic synthesis and optimization for these secure logic circuits. This paper attempts to identify common optimization issues in typical masking-based countermeasures. They include (1) constrained Reed-Muller (RM) logic minimization, (2) minimum decomposition of multi-input AND gates and (3) minimum number of mask bits used to randomize power consumption. An OFDD-based heuristic method is proposed to minimize the RM logic with emphasis on literal number. The latter two optimization problems are formulated as zero-one integer linear programming and graph coloring problems respectively. Based on these formulations and optimizations, an automated design flow for secure cryptographic IC design was implemented in C language.