Uniaxial strained silicon n-FETs on silicon-germanium-on-insulator substrates with an e-Si0.7Ge0.3 stress transfer layer and source/drain stressors for performance enhancement

Abstract

We demonstrate a novel strained Si n-FET where the strain-transfer efficiency of lattice-mismatched source/drain (S/D) stressors is increased significantly by the interaction between an embedded Si0.7Ge0.3 stress transfer layer (STL) and the SiC source/drain (S/D) stressors. The compliance of the SiGe-OI STL caused significant uniaxial tensile strain to be induced in the Si channel. Devices with gate length LG down to 50 nm were fabricated. The strain effects resulted in 59% drive current improvement compared to unstrained Si control n-FETs. In addition, the incorporation of a tensile stress SiN liner improves Id,sat by an additional 10%. Improvement in source-side injection velocity as a result of the lattice interaction between the Si0.7Ge0.3 STL and S/D regions is further investigated.