M. Iijima, M. Kitamura, K. Hamada, K. Fukuoka, M. Numa, A. Tada, S. Maegawa
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引用次数: 3
Abstract
In this paper, we propose an active body-biasing controlled (ABC)-bootstrap PTL (pass-transistor logic) on PD-SOI at 0.5 V-V/sub DD/ for ultra low power design. Applying active body-biasing to bootstrap PTL is the key for higher performance without output voltage loss by boosting gate voltage with coupling capacitance between source and body. Lowering V/sub th/ by body biasing also contributes for high speed operation. Experimental results have shown improvement in both delay time and power consumption.