{"title":"Twice-etched silicon approach for via-last through-silicon-via with a Parylene-HT liner","authors":"B. T. Tung, N. Watanabe, M. Aoyagi, K. Kikuchi","doi":"10.1109/3DIC.2015.7334611","DOIUrl":null,"url":null,"abstract":"In this paper, an alternative fabrication approach to realize a via-last through-Si-via (TSV) for 3D chip stacking is proposed. Two deep silicon etching process (BOSCH) are implemented respectively for TSV's liner and metal layers in order to avoid the critical process to open the contact at the bottom of Si via. Moreover, Parylene-HT is utilized for achieving highly uniformity, high-step-coverage liner. Vias was filled with a solder by a vacuum-assisted filling system. TSVs with dimensions of 6 μm × 22 μm (diameter×height) with 1.5-μm-thick Parylene-HT insulation layer were demonstrated using the proposed approach. Inspection of the fabricated TSV structure is conducted and results are reported.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"184 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC.2015.7334611","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
In this paper, an alternative fabrication approach to realize a via-last through-Si-via (TSV) for 3D chip stacking is proposed. Two deep silicon etching process (BOSCH) are implemented respectively for TSV's liner and metal layers in order to avoid the critical process to open the contact at the bottom of Si via. Moreover, Parylene-HT is utilized for achieving highly uniformity, high-step-coverage liner. Vias was filled with a solder by a vacuum-assisted filling system. TSVs with dimensions of 6 μm × 22 μm (diameter×height) with 1.5-μm-thick Parylene-HT insulation layer were demonstrated using the proposed approach. Inspection of the fabricated TSV structure is conducted and results are reported.
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