Pub Date : 2016-04-20DOI: 10.1109/ICEP.2016.7486827
K. Kondo, Shingo Mukahara, M. Yokoi, J. Onuki
Thermal expansion coefficient(TEC) mismatch between the silicon and copper causes serious problems in on chip and microelectronics packaging. One example is TSV pumping for the via middle process. Higher temperature exposure of 400-600°C during the wiring process causes TSV pumping. The filled copper destroys wiring above TSV. Our additive A shows no pumping of electrodeposited copper TSV. The resistivity of electrodeposited copper TSV after 450°C annealing for the wiring is only 1.09 of conventional electrodeposited copper. Another example is the PCB warpage in solder bumps reflow process. The PCB is initially annealed at 200°C for 60min for the resin solidification. Next, the solder bumps are formed. Then comes the chip and PCB interconnection of 250°C, 10sec with solder bumps retlow. This chip and PCB interconnection annealing at 250°C, 10sec has used to cause PCB warpage. The 34% TEC reduction has been realized at 230 °C . This 34% reduction has been obtained after the second annealing after 200°Cx60min with our additive B. The resistivity of PCB copper after annealing is only 1.32 of conventional electrodeposited copper.
{"title":"No pumping at 450°C with electrodeposited copper TSV","authors":"K. Kondo, Shingo Mukahara, M. Yokoi, J. Onuki","doi":"10.1109/ICEP.2016.7486827","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486827","url":null,"abstract":"Thermal expansion coefficient(TEC) mismatch between the silicon and copper causes serious problems in on chip and microelectronics packaging. One example is TSV pumping for the via middle process. Higher temperature exposure of 400-600°C during the wiring process causes TSV pumping. The filled copper destroys wiring above TSV. Our additive A shows no pumping of electrodeposited copper TSV. The resistivity of electrodeposited copper TSV after 450°C annealing for the wiring is only 1.09 of conventional electrodeposited copper. Another example is the PCB warpage in solder bumps reflow process. The PCB is initially annealed at 200°C for 60min for the resin solidification. Next, the solder bumps are formed. Then comes the chip and PCB interconnection of 250°C, 10sec with solder bumps retlow. This chip and PCB interconnection annealing at 250°C, 10sec has used to cause PCB warpage. The 34% TEC reduction has been realized at 230 °C . This 34% reduction has been obtained after the second annealing after 200°Cx60min with our additive B. The resistivity of PCB copper after annealing is only 1.32 of conventional electrodeposited copper.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123423544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334590
Chao Song, Minxuan Zhang
With the progress of integrated circuit technology, the soft error problem has become more and more serious, which has become a real challenge for reliability design. 3D integrated technology, which is capable of stacking multi circuit layers in the vertical direction, offers the shielding effect to reduce the probability of soft errors. In this paper, we focus on reorder buffer(ROB), and conduct a fine-grained analysis of the AVF of each ROB entry. Based on the non-uniformity of AVF, the ROB is divided into two parts, which statically layout to different circuit layers in 3D chip. Based on the observation that ROB occupancy rate is low at most of the time, we propose a dynamic mapping access pattern and a migration access pattern further to reduce the soft error rate. Simulation results show that the soft error rate was reduced by 47.6%, 84.5% and 88.2% respectively, with the static layout, dynamic mapping and migration access patterns. Considering the correlation analysis on the soft error rate and the capacity of ROB, a better balance between the soft error rate reduction and the area overhead can be achieved if the capacity is 80.
{"title":"Improved access pattern for ROB soft error rate mitigation based on 3D integration technology","authors":"Chao Song, Minxuan Zhang","doi":"10.1109/3DIC.2015.7334590","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334590","url":null,"abstract":"With the progress of integrated circuit technology, the soft error problem has become more and more serious, which has become a real challenge for reliability design. 3D integrated technology, which is capable of stacking multi circuit layers in the vertical direction, offers the shielding effect to reduce the probability of soft errors. In this paper, we focus on reorder buffer(ROB), and conduct a fine-grained analysis of the AVF of each ROB entry. Based on the non-uniformity of AVF, the ROB is divided into two parts, which statically layout to different circuit layers in 3D chip. Based on the observation that ROB occupancy rate is low at most of the time, we propose a dynamic mapping access pattern and a migration access pattern further to reduce the soft error rate. Simulation results show that the soft error rate was reduced by 47.6%, 84.5% and 88.2% respectively, with the static layout, dynamic mapping and migration access patterns. Considering the correlation analysis on the soft error rate and the capacity of ROB, a better balance between the soft error rate reduction and the area overhead can be achieved if the capacity is 80.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129793238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334604
Mohamed N. ElBahey, D. Khalil, H. Ragai
3D integration of digital designs presents an important paradigm shift that introduces several benefits in speed, power, area, and footprint. Significant work has been done so far to enable CAD tools to handle 3D designs and account for TSVs. Yet, it is not as mainstream as conventional planar CAD tools. This work explores enabling existing flow and tools to handle full 3D designs without introducing drastic changes or excessive computations. It focuses on full 3D design STA with routing parasitics for its critical importance in the digital design flow. It proposes and implements an STA framework that efficiently handles full 3D extracted digital designs, as well as, regular planar ones. It presents details on the TSV extraction model, connectivity representation, and delay calculations. The framework can be easily adapted for placement and routing optimizations as well.
{"title":"Proposed static timing analysis framework for extracted 3D integrated circuits (3D-STA)","authors":"Mohamed N. ElBahey, D. Khalil, H. Ragai","doi":"10.1109/3DIC.2015.7334604","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334604","url":null,"abstract":"3D integration of digital designs presents an important paradigm shift that introduces several benefits in speed, power, area, and footprint. Significant work has been done so far to enable CAD tools to handle 3D designs and account for TSVs. Yet, it is not as mainstream as conventional planar CAD tools. This work explores enabling existing flow and tools to handle full 3D designs without introducing drastic changes or excessive computations. It focuses on full 3D design STA with routing parasitics for its critical importance in the digital design flow. It proposes and implements an STA framework that efficiently handles full 3D extracted digital designs, as well as, regular planar ones. It presents details on the TSV extraction model, connectivity representation, and delay calculations. The framework can be easily adapted for placement and routing optimizations as well.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128014512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334602
A. Heinig, R. Fischbach
This paper presents concepts for the implementation of Assembly Design Kits (ADKs) to enable a better assembly and packaging design automation. Both directions of data exchange (from manufacturing to design and vice versa) are important to improve the collaboration between design and manufacturing. A flexible data format is fundamental to reveal manufacturing requirements to a designer as well as to transfer design data into manufacturing.
{"title":"Enabling automatic system design optimization through Assembly Design Kits","authors":"A. Heinig, R. Fischbach","doi":"10.1109/3DIC.2015.7334602","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334602","url":null,"abstract":"This paper presents concepts for the implementation of Assembly Design Kits (ADKs) to enable a better assembly and packaging design automation. Both directions of data exchange (from manufacturing to design and vice versa) are important to improve the collaboration between design and manufacturing. A flexible data format is fundamental to reveal manufacturing requirements to a designer as well as to transfer design data into manufacturing.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131621118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334558
Tomoji Nakamura, Y. Mizushima, Young-Suk Kim, R. Sugie, T. Ohba
Impact of backside thinning damages and topside device structures on the elastic stress distributions in ultra-thinned Si substrates were studied using μ-Raman spectroscopy and TEM observations. The compressive and tensile stresses due to the backside damages and the top-side device structures, respectively, are in equilibrium. The variations in elastic stress depend on the topside device structures such as shallow trench isolations (STIs) and memory-cell transistors, and to a lesser extent on the backside damages. Even for DRAM samples thinner than 4 microns, the elastic deformations underneath STIs and memory-cell transistors areas are considered to be no leakage current degradations, because the relation between retention time and pass rate shows little difference before and after thinning.
{"title":"Characterization of stress distribution in ultra-thinned DRAM wafer","authors":"Tomoji Nakamura, Y. Mizushima, Young-Suk Kim, R. Sugie, T. Ohba","doi":"10.1109/3DIC.2015.7334558","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334558","url":null,"abstract":"Impact of backside thinning damages and topside device structures on the elastic stress distributions in ultra-thinned Si substrates were studied using μ-Raman spectroscopy and TEM observations. The compressive and tensile stresses due to the backside damages and the top-side device structures, respectively, are in equilibrium. The variations in elastic stress depend on the topside device structures such as shallow trench isolations (STIs) and memory-cell transistors, and to a lesser extent on the backside damages. Even for DRAM samples thinner than 4 microns, the elastic deformations underneath STIs and memory-cell transistors areas are considered to be no leakage current degradations, because the relation between retention time and pass rate shows little difference before and after thinning.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131017647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334562
M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, T. Hiramoto
We report on three-dimensionally (3D) integrated circuits and stacked CMOS image sensors by using the direct bonding of silicon-on-insulator (SOI) layers. Since the developed process allows small embedded Au electrodes by damascene process, high-density integration is possible within an image sensor pixel area of a few micrometers, beyond the limit of the conventional technique such as through silicon vias (TSVs). We confirmed a successful operation of the developed 3D integrated circuits with NFETs and PFETs bonded from separate wafers. We also demonstrated stacked CMOS image sensor with pixel-wise 3D integration, which indicates that our technology is promising for high-density integrated circuits and CMOS image sensors.
{"title":"Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers","authors":"M. Goto, K. Hagiwara, Y. Iguchi, H. Ohtake, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, T. Hiramoto","doi":"10.1109/3DIC.2015.7334562","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334562","url":null,"abstract":"We report on three-dimensionally (3D) integrated circuits and stacked CMOS image sensors by using the direct bonding of silicon-on-insulator (SOI) layers. Since the developed process allows small embedded Au electrodes by damascene process, high-density integration is possible within an image sensor pixel area of a few micrometers, beyond the limit of the conventional technique such as through silicon vias (TSVs). We confirmed a successful operation of the developed 3D integrated circuits with NFETs and PFETs bonded from separate wafers. We also demonstrated stacked CMOS image sensor with pixel-wise 3D integration, which indicates that our technology is promising for high-density integrated circuits and CMOS image sensors.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128706535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334612
Cui Huang, Dong Wu, L. Pan, Zheyao Wang
This paper reports fabrication and characterization of TSVs that use combined air-gap/SiO2 as the insulators. Fabrication technologies based on reactive ion etching (RIE) of benzocyclobutene (BCB) sacrificial layers have been developed to fabricate uniform and high aspect-ratio air-gaps, and air-gaps with thickness of 2 μm and aspect-ratio of 25:1 have been successfully fabricated. The measured capacitance-voltage (C-V) and current-voltage (I-V) curves at room temperature and high temperatures show that the TSVs with air-gap/SiO2 liners have low capacitance and leakage current. Compared with the TSVs using a sole air-gap insulator, the additional SiO2 liners protects the TSV from being influenced by the residues of sacrificial materials, and the electrical performance and thermal stability are improved.
{"title":"Air-gap/SiO2 liner TSVs with improved electrical performance","authors":"Cui Huang, Dong Wu, L. Pan, Zheyao Wang","doi":"10.1109/3DIC.2015.7334612","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334612","url":null,"abstract":"This paper reports fabrication and characterization of TSVs that use combined air-gap/SiO2 as the insulators. Fabrication technologies based on reactive ion etching (RIE) of benzocyclobutene (BCB) sacrificial layers have been developed to fabricate uniform and high aspect-ratio air-gaps, and air-gaps with thickness of 2 μm and aspect-ratio of 25:1 have been successfully fabricated. The measured capacitance-voltage (C-V) and current-voltage (I-V) curves at room temperature and high temperatures show that the TSVs with air-gap/SiO2 liners have low capacitance and leakage current. Compared with the TSVs using a sole air-gap insulator, the additional SiO2 liners protects the TSV from being influenced by the residues of sacrificial materials, and the electrical performance and thermal stability are improved.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123196618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334605
Insu Hwang, Jihye Kim, Youngwoo Kim, Jonghyun Cho, Joungho Kim
In glass interposer based 2.5D/3D ICs, through glass via(TGV) noise coupling could critically affect overall system's performance. Therefore it is important to estimate exact noise coupling in glass interposers. Thus noise coupling modeling for glass interposer is needed. We proposed a TGV-TGV noise coupling model based on equivalent circuit model. Our TGV-TGV noise coupling structure for modeling verification is composed of TGVs and channel lines. So we proposed both TGV and channel line coupling model. In this paper, we verified our model using 3D-EM solver in frequency domain up to 20GHz by comparing the s-parameter. We analyzed noise coupling function with our model. Also, noise coupling reduction methods are proposed and their effects are analyzed on frequency domain and time domain.
{"title":"Noise coupling modeling and analysis of through glass via(TGV)","authors":"Insu Hwang, Jihye Kim, Youngwoo Kim, Jonghyun Cho, Joungho Kim","doi":"10.1109/3DIC.2015.7334605","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334605","url":null,"abstract":"In glass interposer based 2.5D/3D ICs, through glass via(TGV) noise coupling could critically affect overall system's performance. Therefore it is important to estimate exact noise coupling in glass interposers. Thus noise coupling modeling for glass interposer is needed. We proposed a TGV-TGV noise coupling model based on equivalent circuit model. Our TGV-TGV noise coupling structure for modeling verification is composed of TGVs and channel lines. So we proposed both TGV and channel line coupling model. In this paper, we verified our model using 3D-EM solver in frequency domain up to 20GHz by comparing the s-parameter. We analyzed noise coupling function with our model. Also, noise coupling reduction methods are proposed and their effects are analyzed on frequency domain and time domain.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121231105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An ultra-fast temporary bonding and release process was investigated for the improvement of 3D integration. The bonding scheme composes of two different kinds of polymer for release layer and adhesive layer. The submicron release layer is a positive photoresist with the characteristic of high UV absorption induced into the de-bonding procedure within 20 s. In addition, the adhesive layer provides robust mechanical strength for the wafer thinning process. Based on results, this structure is a potential candidate for temporary bonding and de-bonding technique in 3D integration.
{"title":"An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration","authors":"Tsung-Yen Tsai, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen","doi":"10.1109/3DIC.2015.7334613","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334613","url":null,"abstract":"An ultra-fast temporary bonding and release process was investigated for the improvement of 3D integration. The bonding scheme composes of two different kinds of polymer for release layer and adhesive layer. The submicron release layer is a positive photoresist with the characteristic of high UV absorption induced into the de-bonding procedure within 20 s. In addition, the adhesive layer provides robust mechanical strength for the wafer thinning process. Based on results, this structure is a potential candidate for temporary bonding and de-bonding technique in 3D integration.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127791847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-23DOI: 10.1109/3DIC.2015.7334583
J. Kawakita, Barbara Horváth, T. Chikyow
Toward fast formation of TSV for 3D-IC or 3D-LSI, a composite with polypyrrole as a conducting polymer and metal silver prepared through the solution photo chemistry was studied with respect to filling status of vertical holes in silicon chip, electrical characteristics and interfacial structures between the filling composite and silicon substrate. Based on the experimental results, the composite was capable of filling within 10 minutes, evaluation procedures of electrical resistance was established and excellent barrier layer was found.
{"title":"Fast filling of through-silicon via (TSV) with conductive polymer/metal composites","authors":"J. Kawakita, Barbara Horváth, T. Chikyow","doi":"10.1109/3DIC.2015.7334583","DOIUrl":"https://doi.org/10.1109/3DIC.2015.7334583","url":null,"abstract":"Toward fast formation of TSV for 3D-IC or 3D-LSI, a composite with polypyrrole as a conducting polymer and metal silver prepared through the solution photo chemistry was studied with respect to filling status of vertical holes in silicon chip, electrical characteristics and interfacial structures between the filling composite and silicon substrate. Based on the experimental results, the composite was capable of filling within 10 minutes, evaluation procedures of electrical resistance was established and excellent barrier layer was found.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133259333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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