{"title":"Vertical Gate-All-Around Tunnel FETs Using InGaAs Nanowire/Si with Core-Multishell Structure","authors":"K. Tomioka, H. Gamo, J. Motohisa, T. Fukui","doi":"10.1109/IEDM13553.2020.9371991","DOIUrl":null,"url":null,"abstract":"We present vertical gate-all-around (VGAA) tunnel FETs (TFETs) using InGaAs nanowire (NW)/Si heterojunction with modulation doped core-multishell NW structures. The NW/Si heterojunction was composed of the axial n+-InGaAs/intrinsic InGaAs NW/p-Si. We investigated effect of using modulation-doped InGaAs/InP/InAlAs/InP core-multishell NW structure for switching performance and showed current enhancement with a steep subthreshold slope (SS). The device exhibited a minimum SS of 21 mV/decade. In addition, the device showed high transconductance efficiency of around 520/V, which exceeded the theoretical maximum limit for conventional FETs (38.5/V). And we demonstrated p-channel switching behavior while maintaining steep SS with same architecture.","PeriodicalId":415186,"journal":{"name":"2020 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM13553.2020.9371991","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
We present vertical gate-all-around (VGAA) tunnel FETs (TFETs) using InGaAs nanowire (NW)/Si heterojunction with modulation doped core-multishell NW structures. The NW/Si heterojunction was composed of the axial n+-InGaAs/intrinsic InGaAs NW/p-Si. We investigated effect of using modulation-doped InGaAs/InP/InAlAs/InP core-multishell NW structure for switching performance and showed current enhancement with a steep subthreshold slope (SS). The device exhibited a minimum SS of 21 mV/decade. In addition, the device showed high transconductance efficiency of around 520/V, which exceeded the theoretical maximum limit for conventional FETs (38.5/V). And we demonstrated p-channel switching behavior while maintaining steep SS with same architecture.
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