Delay Test of Embedded Memories

Abstract

Memory arrays cannot be as easily tested as other storage elements. They can be considered as non-scan cells. Memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these techniques have relatively poor coverage of the timing critical paths. We propose path delay test through memory arrays using pseudo functional test with K Longest Paths Per Gate (PKLPG). Long paths captured into a non-scan cell (including a memory cell) are propagated to a scan cell, and non-scan cells are initialized so that they can launch transitions onto long paths.